2013 Microchip Technology Inc.
Advance Information
DS33030A-page 153
PIC24FV16KM204 FAMILY
TABLE 13-6:
AUTO-SHUTDOWN AND GATING SOURCES
REGISTER 13-3:
CCPxCON2L: CCPx CONTROL 2 LOW REGISTERS
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
PWMRSEN
ASDGM
—
SSDG
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ASDG7
ASDG6
ASDG5
ASDG4
ASDG3
ASDG2
ASDG1
ASDG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PWMRSEN:
CCPx PWM Restart Enable bit
1
= ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input
has ended
0
= ASEVT must be cleared in software to resume PWM activity on output pins
bit 14
ASDGM:
CCPx Auto-Shutdown Gate Mode Enable bit
1
= Wait until the next Time Base Reset or rollover for shutdown to occur
0
= Shutdown event occurs immediately
bit 13
Unimplemented:
Read as ‘
0
’
bit 12
SSDG:
CCPx Software Shutdown/Gate Control bit
1
= Manually force auto-shutdown, timer clock gate or input capture signal gate event (setting of
ASDGM bit still applies)
0
= Normal module operation
bit 11-8
Unimplemented:
Read as ‘
0
’
bit 7-0
ASDG<7:0>:
CCPx Auto-Shutdown/Gating Source Enable bits
1
= ASDGx Source n is enabled (See
for auto-shutdown/gating sources)
0
= ASDGx Source n is disabled
ASDGx Bits
Auto-Shutdown/Gating Source
0
Comparator 1 Output
1
Comparator 2 Output
2
Comparator 3 Output
3
SCCP4 Output Compare
4
SCCP5 Output Compare
5
CLC1 Output
6
OCFA Fault Input
7
OCFB Fault Input
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