2013 Microchip Technology Inc.
Advance Information
DS33030A-page 213
PIC24FV16KM204 FAMILY
REGISTER 19-1:
AD1CON1: A/DA/D CONTROL REGISTER 1
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
ADON
—
ADSIDL
—
—
MODE12
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0, HSC
R/C-0, HSC
SSRC3
SSRC2
SSRC1
SSRC0
—
ASAM
SAMP
DONE
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON:
A/D Operating Mode bit
1
= A/D Converter module is operating
0
= A/D Converter is off
bit 14
Unimplemented:
Read as ‘
0
’
bit 13
ADSIDL:
A/D Stop in Idle Mode bit
1
= Discontinues module operation when device enters Idle mode
0
= Continues module operation in Idle mode
bit 12-11
Unimplemented:
Read as ‘
0
’
bit 10
MODE12:
12-Bit Operation Mode bit
1
= 12-bit A/D operation
0
= 10-bit A/D operation
bit 9-8
FORM<1:0>:
Data Output Format bits (see the following formats)
11
= Fractional result, signed, left-justified
10
= Absolute fractional result, unsigned, left-justified
01
= Decimal result, signed, right-justified
00
= Absolute decimal result, unsigned, right-justified
bit 7-4
SSRC<3:0>:
Sample Clock Source Select bits
1111
= Reserved
1101
= Reserved
1100
= CLC2 event ends sampling and starts conversion
1011
= SCCP4 event ends sampling and starts conversion
1010
= MCCP3 event ends sampling and starts conversion
1001
= MCCP2 event ends sampling and starts conversion
1000
= CLC1 event ends sampling and starts conversion
0111
= Internal counter ends sampling and starts conversion (auto-convert)
0110
= TMR1 Sleep mode Trigger event ends sampling and starts conversion
)
0101
= TMR1 event ends sampling and starts conversion
0100
= CTMU event ends sampling and starts conversion
0011
= SCCP5 event ends sampling and starts conversion
0010
= MCCP1 event ends sampling and starts conversion
0001
= INT0 event ends sampling and starts conversion
0000
= Clearing sample bit ends sampling and starts conversion
Note 1:
This version of the TMR1 Trigger allows A/D conversions to be triggered from TMR1 while the device is
operating in Sleep mode. The SSRC<3:0> =
0101
option allows conversions to be triggered in Run or Idle
modes only.
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