2013 Microchip Technology Inc.
Advance Information
DS33030A-page 215
PIC24FV16KM204 FAMILY
REGISTER 19-2:
AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
PVCFG1
PVCFG0
NVCFG0
—
BUFREGEN
CSCNA
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFS
)
SMPI4
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
(
)
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
PVCFG<1:0>:
Converter Positive Voltage Reference Configuration bits
11
= 4 * Internal V
BG
)
10
= 2 * Internal V
BG
(
01
= External V
REF
+
00
= AV
DD
bit 13
NVCFG0:
Converter Negative Voltage Reference Configuration bits
1
= External V
REF
-
0
= AV
SS
bit 12
Unimplemented:
Read as ‘
0
’
bit 11
BUFREGEN:
A/D Buffer Register Enable bit
1
= Conversion result is loaded into a buffer location determined by the converted channel
0
= A/D result buffer is treated as a FIFO
bit 10
CSCNA:
Scan Input Selections for CH0+ S/H Input for MUX A Setting bit
1
= Scans inputs
0
= Does not scan inputs
bit 9-8
Unimplemented:
Read as ‘
0
’
bit 7
BUFS:
Buffer Fill Status bit
(
)
1
= A/D is filling the upper half of the buffer; user should access data in the lower half
0
= A/D is filling the lower half of the buffer; user should access data in the upper half
bit 6-2
SMPI<4:0>:
Interrupt Sample Rate Select bits
11111
= Interrupts at the completion of the conversion for each 32nd sample
11110
= Interrupts at the completion of the conversion for each 31st sample
00001
= Interrupts at the completion of the conversion for every other sample
00000
= Interrupts at the completion of the conversion for each sample
bit 1
BUFM:
Buffer Fill Mode Select bit
(
1
= Starts filling the buffer at address, AD1BUF0, on the first interrupt and AD1BUF(n/2) on the next
interrupt (Split Buffer mode)
0
= Starts filling the buffer at address, ADCBUF0, and each sequential address on successive
interrupts (FIFO mode)
bit 0
ALTS:
Alternate Input Sample Mode Select bit
1
= Uses channel input selects for Sample A on the first sample and Sample B on the next sample
0
= Always uses channel input selects for Sample A
Note 1:
This is only applicable when the buffer is used in FIFO mode (BUFREGEN =
0
). In addition, BUFS is only
used when BUFM =
1
.
2:
The voltage reference setting will not be within the specification with V
DD
below 4.5V.
3:
The voltage reference setting will not be within the specification with V
DD
below 2.3V.
Summary of Contents for PIC24FV16KM204 FAMILY
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