PIC24FV16KM204 FAMILY
DS33030A-page 252
Advance Information
2013 Microchip Technology Inc.
REGISTER 25-5:
FWDT: WATCHDOG TIMER CONFIGURATION REGISTER
R/P-1
R/P-1
R/P-1 R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
FWDTEN1
WINDIS
FWDTEN0 FWPSA
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7,5
FWDTEN<1:0>:
Watchdog Timer Enable bits
11
= WDT is enabled in hardware
10
= WDT is controlled with the SWDTEN bit setting
01
= WDT is enabled only while the device is active; WDT is disabled in Sleep; SWDTEN bit is disabled
00
= WDT is disabled in hardware; SWDTEN bit is disabled
bit 6
WINDIS:
Windowed Watchdog Timer Disable bit
1
= Standard WDT is selected; windowed WDT is disabled
0
= Windowed WDT is enabled; note that executing a
CLRWDT
instruction while the WDT is disabled in
hardware and software (FWDTEN<1:0> =
00
and SWDTEN (RCON<5>) =
0
) will not cause a
device Reset
bit 4
FWPSA:
WDT Prescaler bit
1
= WDT prescaler ratio of 1:128
0
= WDT prescaler ratio of 1:32
bit 3-0
WDTPS<3:0>:
Watchdog Timer Postscale Select bits
1111
= 1:32,768
1110
= 1:16,384
1101
= 1:8,192
1100
= 1:4,096
1011
= 1:2,048
1010
= 1:1,024
1001
= 1:512
1000
= 1:256
0111
= 1:128
0110
= 1:64
0101
= 1:32
0100
= 1:16
0011
= 1:8
0010
= 1:4
0001
= 1:2
0000
= 1:1
Summary of Contents for PIC24FV16KM204 FAMILY
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