2013 Microchip Technology Inc.
Advance Information
DS33030A-page 285
PIC24FV16KM204 FAMILY
TABLE 27-26: COMPARATOR TIMING REQUIREMENTS
TABLE 27-27: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
FIGURE 27-10:
CAPTURE/COMPARE/PWM TIMINGS (MCCPx, SCCPx MODULES)
TABLE 27-28: CAPTURE/COMPARE/PWM REQUIREMENTS (MCCPx, SCCPx MODULES)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
300
T
RESP
Response Time
(
—
150
400
ns
301
T
MC
2
OV
Comparator Mode Change to
Output Valid
—
—
10
s
* Parameters are characterized but not tested.
Note 1:
Response time is measured with one comparator input at (V
DD
– 1.5)/2, while the other input transitions
from V
SS
to V
DD
.
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Comments
VR310 T
SET
Settling Time
(
—
—
10
s
Note 1:
Settling time is measured while CVRSS =
1
and the CVR<3:0> bits transition from ‘
0000
’ to ‘
1111
’.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
50
T
CLK
L
CCPx Time Base Clock Source Low Time
T
CY
/2
—
ns
TSYNC =
1
31.25
—
ns
TSYNC =
0
51
T
CLK
H
CCPx Time Base Clock Source High Time
T
CY
/2
—
ns
TSYNC =
1
31.25
—
ns
TSYNC =
0
52
T
CLK
CCPx Time Base Clock Source Period
T
CY
—
ns
TSYNC =
1
62.5
—
ns
TSYNC =
0
53
T
CC
L
CCPx Capture or Gating Input Low Time
T
CLK
—
ns
54
T
CC
H
CCPx Capture or Gating Input High Time
T
CLK
—
ns
55
T
CC
P
CCPx Capture or Gating Input Period
2 * T
CLK
/N
—
ns
N = prescale
value (1, 4 or 16)
Note:
for load conditions.
CCPx Time Base
50
51
52
Clock Source
CCPx Capture Input (ICx)
53
54
55
and Gating Inputs
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