2013
Micr
ochip T
e
ch
nol
ogy
I
n
c.
A
d
va
nce Inf
o
rm
at
ion
DS
33030A
-page 55
PIC24FV16KM204 FAMILY
TABLE 4-15:
UART1 REGISTER MAP
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
U1MODE
220h
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1 PDSEL0
STSEL
0000
U1STA
222h
UTXISEL1 UTXINV UTXISEL0
—
UTXBRK UTXEN UTXBF
TRMT
URXISEL1 URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
U1TXREG
224h
—
—
—
—
—
—
—
UART1 Transmit Register
xxxx
U1RXREG
226h
—
—
—
—
—
—
—
UART1 Receive Register
0000
U1BRG
228h
Baud Rate Generator Prescaler
0000
Legend:
x
= unknown,
u
= unchanged, — = unimplemented,
q
= value depends on condition, r = reserved.
Bold
indicates shared access SFRs.
TABLE 4-16:
UART2 REGISTER MAP
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
U2MODE
(
)
230h
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1 PDSEL0
STSEL
0000
U2STA
(
)
232h
UTXISEL1 UTXINV UTXISEL0
—
UTXBRK UTXEN UTXBF
TRMT
URXISEL1 URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
U2TXREG
234h
—
—
—
—
—
—
—
UART2 Transmit Register
xxxx
U2RXREG
236h
—
—
—
—
—
—
—
UART2 Receive Register
0000
U2BRG
)
238h
Baud Rate Generator Prescaler
0000
Legend:
x
= unknown,
u
= unchanged, — = unimplemented,
q
= value depends on condition, r = reserved.
Bold
indicates shared access SFRs.
Note 1:
These registers are available only on PIC24F(V)16KM2XX devices.
Summary of Contents for PIC24FV16KM204 FAMILY
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