PIC24FV16KM204 FAMI
LY
DS3
3030A-page
60
A
d
va
nce Inf
o
rm
at
ion
20
13 M
ic
rochip
T
e
ch
nology
In
c.
TABLE 4-26:
CTMU REGISTER MAP
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CTMUCON1L 35Ah
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN IDISSEN
CTTRIG
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
0000
CTMUCON1H 35Ch EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
—
—
0000
CTMUCON2L 35Eh
—
—
—
—
—
—
—
—
—
—
—
IRSTEN
—
DISCHS2 DISCHS1 DISCHS0
0000
Legend:
x
= unknown,
u
= unchanged, — = unimplemented,
q
= value depends on condition, r = reserved.
Bold
indicates shared access SFRs.
TABLE 4-27:
ANSEL REGISTER MAP
File
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ANSA
4E0h
—
—
—
—
—
—
—
—
—
—
—
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
001F
(
)
ANSB
4E2h
ANSB15
ANSB14
ANSB13 ANSB12
—
—
ANSB9
ANSB8
ANSB7 ANSB6
(
)
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
F3FF
(
)
ANSC
4E4h
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSC2
(
,
)
ANSC1
(
ANSC0
0007
(
)
Legend:
x
= unknown,
u
= unchanged, — = unimplemented,
q
= value depends on condition, r = reserved.
Bold
indicates shared access SFRs.
Note 1:
Reset value depends on the device type; the PIC24F16KM204 value is shown.
2:
These bits are not implemented in 20-pin devices.
3:
These bits are not implemented in 28-pin devices.
TABLE 4-28:
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ALRMVAL
620h
Alarm Value High Register Window Based on APTR<1:0>
xxxx
ALCFGRPT
622h
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1 ALRMPTR0
ARPT7
ARPT6
ARPT5
ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
0000
(
)
RTCVAL
624h
RTCC Value High Register Window Based on RTCPTR<1:0>
xxxx
RCFGCAL
626h
RTCEN
—
RTCWREN RTCSYNC
HALFSEC
RTCOE
RTCPTR1 RTCPTR0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
0000
(
)
RTCPWC
628h
PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1
RTCCLK0
RTCOUT1
RTCOUT0
—
—
—
—
—
—
—
—
0000
(
)
Legend:
x
= unknown,
u
= unchanged, — = unimplemented,
q
= value depends on condition, r = reserved.
Bold
indicates shared access SFRs.
Note 1:
Values are reset only on a V
DD
POR event.
Summary of Contents for PIC24FV16KM204 FAMILY
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Page 315: ... 2013 Microchip Technology Inc Advance Information DS33030A page 315 PIC24FV16KM204 FAMILY ...
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