SA.45s Chip-Scale Atomic Clock
SA.45s CSAC User Guide Revision D
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Figure 13 • Evaluation Board Overview
The following items are included in the developer's kit PCB and power supply.
RF Output (SMA)—The CSAC output is an RF, CMOS 0 VDC–3.3 VDC waveform. A high-speed buffer
(U1) on the evaluation board converts the CMOS output to an AC-coupled output capable of
delivering 10 dBm to a 50 Ω load.
3.3 VDC Jumper—The evaluation board provides regulated 3.3 VDC to the CSAC. In order to allow
convenient measurement of the CSAC power consumption, a jumper is provided in the Vcc
connection to the CSAC. To measure the CSAC current draw, turn off the evaluation board and
install a low-impedance current meter in place of the jumper. Observe proper ESD protocols in
making this measurement.
Replaceable Fuse—Littel fuse part number 0453 01.5.
5 VDC Input—Input power to the evaluation board is provided on a 5 mm (center positive) coaxial
connector (PS1). To avoid damage to the test fixture, it is highly recommended to use only the
power adapter provided by Microsemi with the Developer's Kit.
RS232 Connection (DB9M)—The evaluation board provides a level shifter (U3), which converts the
CSAC 0 VDC–3.3 VDC serial interface to the RS232 standard ±12 V for direct interface with a PC COM
port. Connect the test fixture (J1) to a PC with a standard (non-Null) DB9F-DB9F RS232 cable. To
avoid complication, use the proper cable provided by Microsemi with the developer's kit.
Lock Indicator LED—Indicates normal operation following initial acquisition of the clock signal. This is
the logical complement of the BITE output (CSAC pin 4).
BITE (SMA)—This is a buffered output from pin 4 of the CSAC.
Power Switch—Controls power to the evaluation board and to the CSAC.
Power LED—Indicates the state of the power switch.
Analog Tuning Input (SMA)— This input is directly connected to pin 1 of the CSAC.
1PPS Input (SMA)—The 1PPS input connection to the evaluation board accepts a 1PPS reference of
arbitrary amplitude (logic high: 2 V < V < 20 V) and generates a 0 V–3.3 V CMOS pulse to the CSAC.
IN
This input is capacitively coupled to the level-shifting circuit on the evaluation board (see
) and therefore the applied pulse width must be <10 ms in duration.
1PPS Output (SMA)—The 1PPS output is buffered by a CMOS 0 V–3.3 V logic gate on the evaluation
