SA.45s Chip-Scale Atomic Clock
SA.45s CSAC User Guide Revision D
10
Calibration of the CSAC is a two-step process. First, the CSAC is steered onto frequency, either through
an external
), through 1PPS disciplining (see
!F
"Frequency Steering" (see page 8)
), or with analog tuning (see
"1PPS Disciplining" (see page 12)
the present value of Steer is summed into the non-volatile calibration register through the RS232
Frequency Latch command (see
). Following a Latch
"Frequency Adjustment (F)" (see page 23)
command, the value of Steer is reset to zero.
Note: The Latch command is only valid when the CSAC is locked (Status = 0).
To latch the current steer value to non-volatile storage from CSACdemo, click
.
LATCH
Note: It may be tempting, particularly in disciplining applications, to frequently latch the steering value
into calibration in the event of unforeseen power outage. This is highly discouraged for the following
reason. The lifetime of the CSAC's NV memory is finite; updating it >20,000 times will damage it and
render the CSAC inoperable.
3.3.7
1PPS Output
A CMOS level 1 pulse-per-second (1PPS) output is available on pin 10 upon power-up. The output series
impedance is 200 Ω. The output driver circuit is similar to that of the RF output (see
). Nominal levels are 0 VDC–3.3 VDC. For synchronization purposes, the on-time point is the rising
edge of pin 10.
The 1PPS output is derived by digital division of the RF reference frequency. The frequency stability and
accuracy of the 1PPS output reflects that of the RF output. Consequently, when unlocked (BITE = 1,
status ≠ 0), the 1PPS stability reflects that of the free-running TCXO.
3.3.8
1PPS Synchronization
The 1PPS output is synchronous with one rising edge of the RF output (pin 12). The 1PPS output may be
synchronized with a particular cycle of the RF by applying a synchronization pulse to pin 9. When
synchronized, the counters are reset such that the 1PPS output occurs on the RF rising edge, which is
nearest to the externally-applied rising edge. In this way, the CSAC 1PPS can be synchronized to within
one clock cycle (±100 ns) of the external reference.
The CSAC provides two modes for 1PPS synchronization, Manual and Automatic, which are selected
through a bit in the mode register (see
).
"Set/Clear Operating Modes (M)" (see page 24)
Note: The configuration of the mode register is non-volatile (preserved across power cycles).
3.3.8.1
Manual Synchronization
In Manual Synchronization mode (default), the CSAC ignores any signal present on the 1PPS input line
(pin 9) until commanded through RS232. When a synchronization command is received (see
), the CSAC 1PPS is synchronized to the next rising edge to appear on
Synchronization (S)" (see page 25)
pin 9.
This mode is applicable to configurations where the CSAC is embedded in a system where a 1PPS signal
is always present, but not always reliably accurate or stable (such as a GPS receiver). The host
microprocessor may command the CSAC to synchronize after it has verified the state-of-health of the
1PPS reference source (for example, after querying lock state of the GPS receiver).
To perform manual synchronization from CSACdemo, open the
panel from the
menu. The
1PPS…
View
1PPS panel is shown in the following screen shot.
