SA.45s Chip-Scale Atomic Clock
SA.45s CSAC User Guide Revision D
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Figure 20 • Reference Schematic for Evaluation Board
The 1PPS input on the evaluation board is capacitively coupled to the CSAC through a common collector
transistor stage and a UHS inverter. This is to protect the CSAC in the evaluation environment, from
1PPS signals >5 V.
The 10 MHz output from the CSAC is buffered and capacitively coupled on the evaluation board. It also
offers flexibility to condition the signal as needed by the user.
VCC for the UHS inverter is supplied with a resistor divider and Darlington pair to provide a good filter
for removing 50 Hz–60 Hz AC line noise. However, caution must be taken if designed into a circuit
elsewhere as the output voltage may vary under higher current loads.
3.7.5
Time Error of a CSAC
Time error of any clock is dependent on its operating conditions (temperature and vibration) and the
clocks inherent stability (Aging, ADEV). Time error is given by:
where
E(t): Time error accumulation at time t after initial synchronization
E : Initial time error at t = 0
0
y(t): Fractional frequency of the clock at time t, approximated as
y(t) = y + at + y (t)
0
e
