Hardware Components
UG0209 User Guide Revision 7.1
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4
Hardware Components
4.1
Description and Connections
The SmartFusion Evaluation Kit board is populated with a SmartFusion A2F200-FG484. Following are
the key features of the SmartFusion cSoC.
The microcontroller subsystem (MSS) consists of the following:
•
100 MHz 32-bit ARM Cortex-M3 processor
•
1.25 DMIPS/MHz throughput from zero wait state memory
•
Internal memories
•
Embedded flash memory (eNVM), 64 Kbytes to 512 Kbytes
•
Embedded high-speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, implemented in two physical
blocks to enable simultaneous access from two different masters
•
Multi-layer AHB communications matrix
•
Provides up to 16 Gbps of on-chip memory bandwidth
•
10/100 Ethernet MAC with RMII interface
•
Programmable external memory controller, which supports the following:
•
Asynchronous memories
•
NOR flash, SRAM, PSRAM
•
Synchronous SRAMs
•
Two I
2
C peripherals
•
Two 16550 compatible UARTs
•
Two SPI peripherals
•
Two 32-bit timers
•
32-bit watchdog timer
•
8-channel DMA controller
•
Clock sources
•
1.5 MHz to 20 MHz main oscillator
•
Battery-backed 32 KHz low power oscillator with real-time counter (RTC)
•
100 MHz embedded RC oscillator 1% accuracy
•
Embedded PLL with 4 output phases
•
High-performance FPGA
•
Based on Microsemi's proven ProASIC
®
3 FPGA fabric
•
Analog front-end (AFE)
•
Up to three 12-bit SAR analog-to-digital converters (ADCs)
•
One first-order
(sigma delta) digital-to-analog converter (DAC) per ADC
•
Up to 5 new high-performance analog signal conditioning blocks (SCB) per device
•
Two high-speed comparators
•
Analog compute engine (ACE)
•
Offloads CPU from analog initialization and processing of ADC, DAC, and SCBs
•
Sample sequencing engine for ADC and DAC parameter setup
•
Post-processing engine (PPE) for functions such as low-pass filtering and linear transformation
