System Core, Boot Configuration and On-Board Memory 5
miriac SBC-T1024 User Manual
V 2.3
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© MicroSys Electronics GmbH 2017
5
System Core, Boot Configuration
and On-Board Memory
5.1
Processor NXP T1024
The T1024 Processor by NXP is a QorIQ Power Architecture CPU with two CPU
cores. It exposes a wide variety of external interfaces, which are explained in detail
in the following chapters. Each core has a private 256KB L2 cache. Furthermore,
256KB shared L3 CoreNet platform cache is offered.
The two CPU cores run at a maximum clock speed of 1400 MHz, 1200 MHz or
1000 MHz respectively, depending on the ordered type. The CPU frequency can
be clocked down if necessary.
5.2
JTAG Chain
The JTAG chain of the SBC-T1024 includes the T1024 processor only. The JTAG
port is directly connected to the connector
“JTG0”.
The JTAG connector footprint provides JTAG signals. For interfacing standard de-
bugger pinouts an additional intermediate adapter is necessary.
Please see chapter
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for a d
escription of the JTAG connector.
5.3
Reset Structure
Figure 5-1 Reset Structure (carrier CRX05 Revision 2)
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