System Core, Boot Configuration and On-Board Memory 5
miriac SBC-T1024 User Manual
V 2.3
26/70
© MicroSys Electronics GmbH 2017
Table 5-2 Voltage monitoring limits (carrier)
5.4
Clock Distribution
The following diagram shows the clock distribution of the SBC-T1024 system
T1024
ST4
ST1
Pin
Name
Signal
Pin
Signal
Pin
K1
SDHC_CL
K
→
10R
→
SDC-
CLK
B100
→
→
→
SDC-CLK-
EMI
5
W1
IIC1_SCL
→
→
→
I2C1-
SCL
B78
→
→
→
See chapter 5.8.1
V3
IIC2_SCL
→
→
→
I2C2-
SCL
B75
→
→
→
See chapter 5.8.2
JTG0
E18
TCK
→
→
→
JTCK
B105
→
10R
→
JTCK
6
J14
AF3
EC1_TX_
CLK
→
10R
→
MII1-
TXCK
T94
→
→
→
TX_CLK
53
AD1
EC1_RX_
CLK
←
10R
←
MII1-
RXCK
T86
←
10R
←
RX_CLK
46
AG3
EC1_GTX
_CLK125
←
10R
←
MII1-
CRS
T83
←
←
←
CLK125
9
ST15
M4
DIU_CLK_
OUT
→
10R
→
DIU-
CLK
B54
→
→
→
DIU-CLK
26
N1
SPI_CLK
→
10R
→
SPI-
CLK
B69
→
→
→
SPI-CLK
11
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