System Core, Boot Configuration and On-Board Memory 5
miriac SBC-T1024 User Manual
V 2.3
29/70
© MicroSys Electronics GmbH 2017
5.6
NAND Flash
The SBC-T1024 system is equipped with 2GB of NAND Flash by default. Different
sizes may be available on request/order. The following table shows the
connections and signal levels for the NAND Flash.
I/O
Range
NAND Flash
SBC-
T1024
T1024
Description
Pin
Name
Signal
Pin
Name
1,8V
G5
LOCK
Lock
1,8V
C8
RY/BY
→
NAND-
RB#
→
B15 /
A15
IFC_RB0# /
IFC_RB1#
ready/busy,
10K pullup
1,8V
D4
RE#
←
IFC-OE#
←
D15
IFC_OE#
read enable
1,8V
C6
CE#
←
NAND-
CS#
←
C13 /
E15
NANDF_CS0
chip select
1,8V
D3,G4,H8,
J6
VCC
+1.8V
C5,F7,K3,
K8
GND
GND
1,8V
D5
CLE
←
IFC-CLE
←
F16
IFC_CLE
command
latch enable
1,8V
C4
ALE
←
IFC-AVD
←
D17
IFC_AVD
address latch
enable
1,8V
C7
WE#
←
IFC-WE#
←
D13
IFC_WE0#
write enable
1,8V
C3
WP#
←
IFC-WP#
←
F17
IFC_WP0#
write protect
1,8V
H4
D0
↔
IFC-AD7
↔
A4
IFC_AD0
data line
1,8V
J4
D1
↔
IFC-AD6
↔
B5
IFC_AD1
data line
1,8V
K4
D2
↔
IFC-AD5
↔
A5
IFC_AD2
data line
1,8V
K5
D3
↔
IFC-AD4
↔
B6
IFC_AD3
data line
1,8V
K6
D4
↔
IFC-AD3
↔
A6
IFC_AD4
data line
1,8V
J7
D5
↔
IFC-AD2
↔
A7
IFC_AD5
data line
1,8V
K7
D6
↔
IFC-AD1
↔
B8
IFC_AD6
data line
1,8V
J8
D7
↔
IFC-AD0
↔
A8
IFC_AD7
data line
G3
n.c.
Not connect
G8
n.c.
Not connect
Table 5-5 NAND Flash pin assignments
The MPX-T1024 module as part of the SBC-T1024 system provides two chip selects
for the parallel IFC bus. They are routed to the extension connector on the MPX-T1024
module and to the NAND flash. As only CS0# is available as boot chip select, CS0#
and CS1# are multiplexed depending on the boot device selected by the BOOT-SELx
pins (see chapter 5.5 and 7)
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