System Core, Boot Configuration and On-Board Memory 5
miriac SBC-T1024 User Manual
V 2.3
32/70
© MicroSys Electronics GmbH 2017
The I²C Bus 1 has the following layout:
I/O Range: LVTTL
Device
SCL
(Signal Name)
Pin
SDA
(Signal Name)
Pin
T1024
IIC1_SCL
W1
IIC1_SDA
V1
↓
↕
LM95245
SCK
7
SDA
8
↓
↕
AT24C128C
SCL
6
SDA
5
↓
↕
RX-8803LC
SCL
5
SDA
8
↓
↕
IDT6V49205B
SCLK
46
SDATA
47
↓
↕
Module Connector
I2C1_SCL
B78
I2C1_SDA
B77
↓
↕
MAX7325
SCL
19
SDA
20
↓
↕
BR24G128NUX-3
SCL
6
SDA
5
↓
↕
TLC59116IRHBR
SCL
25
SDA
26
Table 5-8 I²C-1 pin assignment
5.8.2 I2C-2
I²C Bus 2 (7-Bit address):
Address
Device
Function
0x28
SC18IS602BIPW
I2C to SPI Bridge
0x70
TCA9544APWR
I²C Multiplexer
(for I²C ports on PCIe slots)
0x73
MAX9611AUB
(not populated by default)
Current Monitor for module consumption
Table 5-9 I²C2 bus map
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