MITS 8800b-dm, Documentation

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Page 3: ...B i w r a m i M a subsidiary of Pertoc C o m p u t e r Corporation 2450 Alamo S E Albuquerque New Mexico 87106 ...

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Page 5: ...Computer Corporation Microsystems Division Marketing Headquarters Pertec Computer Corporation Microsystems Division 20630 Nordhoff Street Chatsworth CA 91311 Phone 213 998 1800 TWX 910 494 2788 International Marketing Headquarters Pertec Computer Corporation Business Systems Division 17112 Armstrong Avenue Irvine CA 92714 USA Phone 714 540 8340 TWX 910 595 1912 ii ...

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Page 7: ...CHANGE RECORD Revision Date Pages A June 1978 Initial Release m ...

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Page 9: ...key Module 40 3 3 AUTO START 54 3 4 Miscellaneous Options 55 3 5 The Power Supply 57 4 Troubleshooting Hints 59 4 1 Introduction 61 4 2 Preliminary Considerations 61 4 3 CPU 62 4 4 Turnkey Module 62 Part III Minidisk System 1 Introduction 67 1 1 MITS Altair Minidisk System Description 69 1 2 Specifications 69 2 Theory of Operation 73 2 1 General 75 2 2 Logic Circuits 75 2 3 Schematic Referencing 7...

Page 10: ...15 Disk Disable Timer 104 2 16 Move Head Status 104 2 17 Head Status 105 2 18 Enable Interrupts 105 3 Preliminary Checkout 107 3 1 Disk Enable Test 109 3 2 Altair Minidisk Controller Timing Test Points 110 3 3 Altair Minidisk Test Programs 123 Appendices A Altair 8800b Bus Assignments 125 B Minidisk Programming 129 Intel 8080 Microcomputer System User s Manual 143 248067A ...

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Page 13: ...d operation manual which details procedures for expanding and modifying the standard system Section 4 is a brief guide to troubleshooting the electronics of the computer The Minidisk mass storage subsystem consists of one or two Minidiskk drives a drive controller and an interface card for connecting the disk system to the computer These are all described in Part III of this documentation package ...

Page 14: ...ctions printed on the tabs The computer is set at the factory to match the terminal shipped with it Therefore to install the terminal it is only necessary to connect the computer and the terminal with the cable supplied with the terminal The diagram below shows the 25 pin cable connectors and the matching connectors on the terminal and computer Figure 1 1 25 Pin Cable Connectors The power supply i...

Page 15: ...itions At 12 o 1 clock the unit is off and the key may be removed At 3 o clock the power is on and the front panel switches are enabled At 6 o clock the computer is on but the front panel switches are disabled In this position the key may be removed With the power switch on the Power indicator should light showing that the computer circuitry is receiving operating voltage from the power supply If ...

Page 16: ...no printer is connected any of the letters may be typed If the response is not 0 C or Q however BASIC asks LINEPRINTER again BASIC now asks HIGHEST DISK NUMBER In a system with 1 disk the highest number is 0 With 2 disks the highest number is 1 Typing just a carriage return is equivalent to typing 0 Now BASIC asks the number of disk data files random access and sequential to be open at one time HO...

Page 17: ...s type the foil owing command LOAD program name disk number where program name is the name of the desired program and disk number m is the number of the disk drive into which the BASIC disk was inserted usually zero To avoid inadvertant damage to the BASIC disk type the following command UNL0AD disk number where disk number is the drive number that appeared in the LOAD command above Now the BASIC ...

Page 18: ...C reads these marks to determine sector boundari es CAUTION Only new blank diskettes need to be initialized Using DSKINI on a diskette that contains files destroys all the files DISKINI should therefore be used with extreme caution The DSKINI process takes about 2 minutes per diskette When it is finished BASIC prints OK D Mounting Diskettes To ready a diskette for reading or writing type the foil ...

Page 19: ...to their storage envelopes when they are not in use Do not leave them in the drive 2 Keep diskettes away from magnetic fields Fields may be caused by fluorescent lights transformers or large pieces of magnetizable materials 3 Mark the diskette label only with felt tip pen Do not use ball point pen or pencil 4 Keep dust and other particulate matter away from diskettes 5 Keep diskettes away from exc...

Page 20: ...rd disconnected from the line To remove the case cover remove the two bolts in the upper corners of the back panel Then slide the cover back and lift it off To remove a card pull straight up on both ends of the card Carefully remove any cable connectors when the board is free To insert a card connect the necessary cables and position the board so the edge connector is down and the component side o...

Page 21: ...o a different device or otherwise changed set the desired address data transfer rate and s ignal type p 42ff 4 If the new device is to be the console terminal for BASIC or DOS set the sense switch on the Turnkey module board to conform to the device p 41 and BASIC or DOS manual C Adding Special PROM Functions The Turnkey Module has sockets for up to four 256 byte PROM chips These PROMs can be used...

Page 22: ... the PROM or AUTO START addresses will disable this feature p 54 NOTE A Turnkey PROM Monitor is a good investment for an ex panded system The Monitor allows examination and modi fication of any memory location from the terminal It lets the operator dump the contents of any range of memory loca tions and transfer control of the computer s execution to any address Putting the Monitor at the AUTO STA...

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Page 27: ...will RAM is volatile however and information is lost when power is interrupted Programmable Read only memory PROM is non volatile Information in PROM is always present whether the power is on or not Thus PROM can store programs and data which must be permanently retained The computer cannot write information into PROM however A special PROM programmer must be used to do this although factory progr...

Page 28: ...ystem bus on the motherboard The bus is fully parallel meaning that all signals are available to all boards plugged into the motherboard s sockets This allows for easy and quick system expansion The motherboard can accommodate the CPU and Turnkey Module boards plus up to 16 additional boards The Power Supply provides all the power voltages required by the Altair 8800b Turnkey system components The...

Page 29: ...Figure 1 4 Front Panel Switches and Indicators 248067A 19 14 Blank ...

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Page 33: ...e ability to change the order in which its instruction are executed and to modify the instructions themselves This accounts in part for the great flexibility of stored program computers As the diagram shows the Control and Processor elements are the heart of the system All the other elements of the system communicate with and are controlled by the Control and Processor In many computers including ...

Page 34: ...ts The pins of each board are connected directly to the corresponding pins of every other board As a result the system is easily expandable since every board has access to all of the data addresses status and control information in the system The bus is located physically on a 100 conductor printed circuit motherboard The printed circuit card edge connectors on the motherboard provide mechanical s...

Page 35: ...during a Memory Write In an I O cycle the Address bus carries the address of the I O port through which the data transfer is to take place The port address is only eight bits long so it is carried both in the high and low order bytes of the 16 bit Address bus The Data in bus carries information from the port to the CPU during an Input cycle Similarly the Data out bus carries information from the C...

Page 36: ...ld state the CPU is effectively disconnected from the bus This allows a direct memory access device if it is used to take control of the bus and transfer information directly to and from memory For more information on machine cycles see the Intel 8080 machine cycles see the Intel 8080 Microcomputer System User s Manual abbreviated IMSUM section 2 pp 3 11 2 2 The CPU Board NOTE In the following des...

Page 37: ...EG 8C IUF 50 100 6RD L6 VBB 5V REG REF DESiG TYPE VCC GRO OTHER REF DESIG TYPE VCC GRD OTHER M 8080A 2 0 2 G B 74LS04 14 7 J X R V N U P 74368 OR 8T98 16 8 C 74LSI3 OR 74LS20 14 7 J X R V N U P 74368 OR 8T98 16 8 C 74LSI3 OR 74LS20 14 7 K 8212 24 12 S Y 74LSI4 14 7 D E 8216 16 8 F 8224 16 8 V D D 9 P W 74367 16 8 A 4 0 0 9 1 8 VDO 16 Figure 2 3b CPU Board Power Regulators ...

Page 38: ...ed to load the 8212 status latch The READY signal is the logical product AND of bus signals XRDY PRDY XRDY2 and FRDY Normally only PRDY is used for memory synchroni zation the others are set to logical 1 by pullup resistors The bus signal PRESET is filtered lengthened shaped and synchronized by the 8224 to generate the RESET input for the 8080A The STSTB signal is generated as soon as the status i...

Page 39: ...try Unused lines are pulled HIGH by resistors which also allow any one of several boards to pull any input line LOW A line is normally pulled LOW either by an open collector driver or a tri state driver with the condition that no more than one tri state driver may be enabled at one time Examples of these input lines are PINT and PHOLD in zone D 8 the READY lines PRDY etc in zone A 7 PRESET in zone...

Page 40: ...us 2 An address of a byte in RAM is detected by IC B The output of IC B is active if a start sequence is not in progress and the current machine cycle is not an I O cycle or an interrupt Therefore the only time a RAM address is detected is when the machine cycle is a memory cycle or a Halt cycle The output of IC B enables the RAM ICs and the data bus interfaces P and R The direction of the data bu...

Page 41: ...y a multiplexer ICs M and N which is controlled by flip flops Ta Sa and Sb The flip flops are cleared by PRESET a bus signal derived from POC or generated by the START switch on the front panel Subsequent PDBIN pulses cause the flip flops to change from one state to the next as shown in the sequence diagram Figure 2 6 The pulses generated by the flip flops cause the multiplexer to choose one of th...

Page 42: ...PRESET low PDBIN Ta Sa Sb 0 0 0 Ta Sa Sb 1 1 1 PDBIN PDBIN Ta Sa Sb 0 1 0 PDBIN PDBIN Ta Sa Sb 0 0 1 Ta Sa Sb 1 1 0 Figure 2 6 AUTO START Logic Control State Diagram 32 248067A ...

Page 43: ...oes LOW and memory instructions can be fetched C Sense Switches The sense switch circuitry is shown in Figure 2 4 a and b IC K Figure 2 4a detects I O port address 255 decimal 377 octal which is reserved for the sense switches The output active LOW enables the tri state buffers connected to the sense switches Figure 2 4b putting the bits represented by the switch positions on the bidirectional bus...

Page 44: ...monitors the 5 volt supply on the Turnkey Module The bus signal PRDY is grounded when the RUN STOP switch is in the STOP position PRESET is grounded momentarily by the START switch which in turn initiates the AUTO START sequence Contact bounce is filtered out on the CPU board to generate a reset signal suitable for the CPU F Miscellaneous Signals Several miscellaneous signals are handled by the re...

Page 45: ...le power regulator circuitry is shown in Figure 2 4a The 5 volt supply is derived from the 8 volt line by an IC regulator The 9 volt supply comes from the 18 volt line through a zener regulator and the 0 volt supply is derived by a transistor zener regulator from the 18 volt line Figure 2 7 is the schematic for the power circuits in the 8800b case The 18 and 18 volt supplies are pre regulated The ...

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Page 49: ... is moved to the STOP position Moving the switch back to RUN continues execution at the point where it was stopped When actuated stops execution When released starts execution at the START address selected by switches on the Turnkey Module If the switch is actuated when the RUN STOP switch is in the STOP position the computer stops in the middle of the START sequence Moving RUN STOP to RUN continu...

Page 50: ...nkey Module board Figure 3 1 In operation the most significant 6 bits of the incoming address are compared with the settings of the switches If they match the remaining 10 bits are decoded to select the proper byte in that block RAM ADDRESS TURNKEY MODULE 15 14 13 1 2 11 10 15 14 PROM 13 ADDRESS 11 10 SWl SW2 SW3 figure 3 1 RAM and FRCM Address Switches 4Q 248067A ...

Page 51: ... eight sense switches on the Turnkey Module representing one byte of data This byte may be read by program instructions and used as data or to select options in the program Sense switch settings are described in the documentation for the software products such as Altair BASIC that use the switches Moving the Turnkey Module sense switches in the direction of the silk screened arrow next to the swit...

Page 52: ...the SIO address switch settings If they match the channel is enabled The least significant bit selects the Data bit zero l or Status Control bit zero 0 port To set the switches convert the desired address to binary Move each switch in the direction of the silk screened arrow to represent one and in the opposite direction for zero Switch 7 represents the most significant bit SIO CONNECTOR pin is nn...

Page 53: ...loaded during an Output Operation S S S S S S S l 7 6 5 4 3 2 1 Receive Data Buffer Data is stripped of parity Transmit Data Buffer S 7 S 6 S 5 S 4 S 3 S 2 S 1 0 Status Control S j through Sy refer to the binary representation of the positions of the SIO address select switches ...

Page 54: ...m a modem goes LOW to indicate that a carrier is not present the Data Carrier Detect bit is set to 1 This setting causes an Interrupt Request to be generated if the Receive Interrupt Enable bit is set After the DCD input returns HIGH DCD remains one until it is reset either by reading first the Status Register and then the Data Register or by a master reset If the DCD input remains LOW after the S...

Page 55: ...s selected then both the transmitter parity generator output and the receiver parity check results are inhibited h Interrupt Request IRQ bit 7 IRQ indicates the state of the IRQ signal Any interrupt condition with its applicable enable is indicated in this status bit Anytime the IRQ signal is LOW the IRQ bit is one to indicate the interrupt or service request status Section 2 2 C 4 shows how to ju...

Page 56: ...op bit 1 0 0 8 bits two stop bits 1 0 1 8 bits one stop bit 1 1 0 8 bits even parity one stop bit 1 1 1 8 bits odd parity one stop bit c Transmitter Control bits 5 and 6 Two Transmitter Control Bits provide for control of the interrupt from the Transmit Data Register Empty condition the Request to Send output and the transmission of a break level space The setup of interrupt jumpers are shown in S...

Page 57: ...ems not using the Vector Interrupt board the signal IRQ may be connected to the PINT line Then if an SIO interrupt occurs PINT will be pulled LOW until the condition that caused the interrupt no longer exists If the Interrupt Enable bit in the CPU is set then a RST 7 instruction is forced into the instruction sequence Interrupt signals from other I O cir cuits may also be connected to the PINT lin...

Page 58: ...acters are handled The bit rate is selected by jumpers and by Control Register bits 1 and 0 Table 3 B shows the resultant bit rate for every usable combination of jumpers and control bits The jumpers S0 SI S2 and S3 are shown in Figure 3 3 If CR0 and CRT are both zero and the external rate is not selected then the SIO may only be used for transmission Otherwise the SIO may be used for both receivi...

Page 59: ...O 0 CRl 1 slow 64 counter selected CRO 0 CRl 0 sychronous data 1 counter selected 110 27 5 1760 X 150 37 5 2400 X 300 75 4800 X X 2400 600 38400 X 1200 300 19200 X X 1800 450 28800 X X 4800 1200 76800 X X X 9600 2400 153600 X 2400 600 38400 X X 600 150 9600 X X 200 50 3200 X X X 134 5 33 375 2152 X X 75 18 75 1200 X X X 50 12 5 800 X X X X X X X External 16 rate 36 000 max External 64 rate 9000 ma...

Page 60: ...nnector on the Turnkey Module to the rear panel The rear panel connector is the industry standard 25 pin data communications connector Table 3 C Signal Type From To Notes TTY Compatible XI K4 K3 K2 X2 P5 P3 P2 RS232 Compatible X3 K3 K2 X4 P3 P2 Put in only if DCD signal is not used Put in only if CTS signal is not used TTL Compatible 3 2 mA max load 16 mA min drive X2 K4 K3 K2 K1 X3 P4 P3 P2 PI No...

Page 61: ... loop terminals The terminal s instruction book should be consulted for the proper choice of signal types Table 3 D From Molex To 25 Pin Connector Pin Number Function Female Male Female Pin Number Function TTY Cable RS232 Cable TTL Cable 1 TTL RTS 6 4 2 TTY XMIT 3 3 TTY REC 4 4 All REC 5 2 2 5 DCD 8 8 6 CTS 5 5 7 XTERNAL CLOCK 15 15 8 GND 2 7 7 9 RS232 RTS 4 10 RS232 TTL XMIT 3 3 243G67A 51 ...

Page 62: ...ader cover The cover can now be removed The interconnection between the computer s SIO and the Teletype is shown in Figure 3 5 Connection is made to terminal strip 1514111 which is at the right rear of the Teletype 25 PIN CONNECTOR FEMALE MALE CABLE 3 f 0 d n P U R P L E Y E L L O W Q BLACK GREEN 7 I T V W H I T E B R O W N R E D G R E E N fi CV WHITE YELLOW WHITE BLACK V W H I T E B L U E BROWN Y...

Page 63: ...for local mode should be connected as 1450 ohms This resistor is on the right hand side of the Teletype halfway back After the connections and modifications are made replace the cover faceplate knobs paper roll and screws Be sure that the Turnkey Module and the internal cable have been set up for TTY I O 3 For RS 232 input output the cable is wired as shown in Figure 3 6 Note that the cable is sym...

Page 64: ...switch is released the start sequence logic forces the CPU to begin executing instructions at an address selected by a set of switches on the Turnkey Module The switches are shown in Figure 3 7 D CZJ a a CD 1 Figure 3 7 AUTO START Address Switches 54 248067A ...

Page 65: ...If the 8800b Turnkey Monitor PROM is installed the AUTO START address must be 176400 octal Therefore all the AUTO START switches except switch 9 must be in the 11 1 position 3 4 Miscellaneous Options A Use of Turnkey Module with Front Panel Model The Turnkey Module may be used in the standard full front panel model of the Altair 8800b computer To do this the following jumpers must be removed from ...

Page 66: ...Power On START switch AUX CLR pulse Alternate 2 ON to SW Power On START switch POC pulse START PoiT pulse START Alternate 3 ON to SW SB to C Power On START switch POC pulse START Alternate 3 ON to SW SB to C Power On START switch AUX CLR pulse POC pulse START Alternate 3 ON to SW SB to C Power On START switch AUX CLR pulse Alternate 4 SA to SW ON to C Power On START switch POC pulse START Alternat...

Page 67: ...The 18 and 18 volt supplies are pre regulated but the 8 volt supply must be adjusted for differing loads by moving the tap on the power transformer secondary The trans former secondary taps are shown in Figure 3 9 The correct secondary tap REAR PANEL I I I I I I l l l l l l l l l l i l l l l i l l l l i l l l l l l l l l i l l l l l l l l l l l l l l l l l l l l l l l l l l l M l l l i l l l l l l...

Page 68: ...erboard 4 If the measured voltage is greater than 9 volts the next lower tap should be used if it is available If the voltage is less than 7 5 volts the next higher tap should be used Be sure to dis connect the power cord before moving the transformer tap connection B Power Supply capacity The power supplies can power most systems that can be accommodated in the case Only an unusually large system...

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Page 71: ...ds Troubleshooting optional memory and I O boards is covered in the manuals for those boards The directions in these manuals often assume that a full front panel is used presenting test loops to be executed in the single step mode If a full front panel is not used use a logic analyzer and a test program instead C Trouble Follows Change An error in system change jumper instal lation repair or board...

Page 72: ...CPU 5 5 5 5 5 5 Turnkey 9 10 Module 9 1 0 volt 0 5 volt D Check the clock on the CPU board This may be monitored at IC 0 pin 3 The correct frequency is 2 0 MHz 4 3 CPU The CPU board requires less troubleshooting than the circuits on the Turnkey Module When troubleshooting the CPU monitor TTL buffered signals rather than MOS driven signals as much as possible to avoid loading the 8080A IC When moni...

Page 73: ...trouble in the wait state logic and incorrect address setting C RAM Correctly functioning RAM can be read from and written into from the front panel The most common RAM problems are incorrect setting of the starting address switches and bad RAM ICs D Sense Switches Because software uses the sense switches to make decisions trouble with the sense switches may look like trouble elsewhere The front p...

Page 74: ...e problem is in the transmitter or the receiver 2 The output of the baud rate generator can be checked at pin 10 of IC G It should be a square wave with a frequency 16 times the selected baud rate For verification on the oscilloscope the periods for some popu lar baud rates are shown below Baud Rate Clock Period 110 568 s 300 208 is 1200 52 us 3 The most common sources of SIO problems are incorrec...

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Page 79: ...imer turns the drive motor off if the system has not been accessed for more than three seconds This helps increase motor life The address of each drive is set by switch SW 1 on the drives buffer address circuitry board This board is physically attached to the drive by spring clips The drive addresses are set at the factory 0 for a single drive 0 and 1 for dual drives but the addresses may be chang...

Page 80: ...rformance Specifications a Data Capacity Hard Sectored Format Per Minidiskette 71 680 Data Bytes Per Track 2 048 Data Bytes Per Sector 128 Data Bytes b Data Transfer Rate 125 000 Bits Per Second c Access Time Disk Enable to READ or WRITE Function of motor start up time 1 sec min Track to Track 50 ms Average Access Time including motor start up time 1 85 sec Worst Case Access Time 2 9 sec Worst Cas...

Page 81: ...bits READ Hard unrecoverable errors 1 per 1 0 bits READ b MTBF 8000 Hrs 2535 motor run time c Service Life 5 years d Media Life 3 0 x 10 6 Passes Track 4 Power Requirements a Minidisk Drive Standby 25 watts typical m v o r 2 2 Q V 6 Q H Z Q r 5 Q H Z Operating 35 watts typical 248067A 71 60 Blank ...

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Page 85: ...yed by small circles A small circle at an input to a logic circuit indicates that the input is an active LOW that is a LOW signal will enable the input A small circle at the output of a logic circuit indicates that the output is an active LOW that is the output is LOW in the actuated state A bar over the signal description also indicates an active LOW Conversely the absence of a small circle on th...

Page 86: ...e LOW Inverter A 0 A A C J The inverter is a device whose output is the opposite state of the input Non Inverting Bus Driv A A A C sr When enabled the non inverting bus driver is a device whose output is the same state as the input Data is enabled through the device by applying a LOW signal to the E input The output floats 11 or goes to a high impedance state when the non inverting bus driver is n...

Page 87: ...4L75 4 C 0 4 accx u When the clock is HIGH information present at data inputs D O j is transferred to the outputs Oata is latched on the falling edge of the clock pulse The data is inverted when the outputs are used Dual J K Master Slave FT ip Flop 74L73 or 74LS73 When inputs are conditioned with J HIGH and K LOW and the flip flop is clocked at C the Q output either goes or remains HIGH but cannot...

Page 88: ...llel Out Serial In Shift Register 74164 Clocking occurs on a LOW to HIGH transition of the clock input shifting the data over one position A LOW at either or both inputs inhibits entry of new data and resets the flip flop LOW on the following clock pulse When both inputs are HIGH the A output is HIGH Edge Triggered D Type Flip Flop 74L74 Applying a LOW signal to the clear input CLR resets the flip...

Page 89: ... clock pulse 8 Bit Parallel In Serial Out Shift Register 74166 Serial Data Out O R ri ocx SER PAR CLOCK INHIB SER PAR Parallel Data In 3 1 I t 2 1 3 4 5 61 7 When HIGH the SER 0PAR input enables the serial data input when LOW the parallel data inputs are enabled During parallel loading 2 7 serial data flow SERIAL DATA OUT is inhibited When clock inhibit CLOCK INHIB is held HIGH clocking is inhibit...

Page 90: ...idisk Extended BASIC 2 Two Controller boards which interface the Altair 8800 computer to the Disk Drive see Disk Controller Theory of Operation beginning with paragraph 2 5 3 The Disk Drive assembly which contains the Minidisk drive plus the line drives and receivers necessary for interconnection to the Controller and additional Disk Drives MINIDISK SYSTEM BLOCK DIAGRAM Figure 2 1 Minidisk System ...

Page 91: ...Sector number with the Sector count from the Controller circuit After the Disk reaches the correct rotational position or Sector the Altair computer performs either a Read Data function Input Channel 012g D0 D7 or enters a Write Data mode In the Write mode the Write Circuits must be enabled Output Channel 011g D7 1 A few hundred micro second delay elapses before Write Data is requested after which...

Page 92: ... the respective enable line from the address select cir cuit Board 1 OCL WOS COS ROS S T A T U S STR OBE SECTOR S T R O B E Figure 2 2 I O Channel Timing The three Output functions associated with Minidisk Board 2 are 1 Output on Channel 0108 DISK CONTROL LATCH DCL selects Disk address and enables Controller 2 Output on Channel 011g CONTROL DISK CD controls Disk Drive functions such as STEP IN or ...

Page 93: ...ion includes HEAD STATUS CHS OK TO MOVE HEAD MH ENTER NEW WRITE DATA ENWD NEW READ DATA AVAILABLE NRDA Places the Disk Sector count on the Altair Data Bus As the Disk rotates the Sector count is incremented every 12 5ms and is reset to 0 upon detec tion of the Index hole once every rotation 200ms Places Disk READ DATA on the Altair Data Bus This input instruction resets the NRDA Status bit 248067A...

Page 94: ... BOARD I Figure 2 3 Disk Controller Block Diagram Sheet 1 External Connections and Address Select ...

Page 95: ...BOARD I Figure 2 4 Disk Controller Block Diagram Sheet 2 Internal Connections ...

Page 96: ...on an output to Channel 012g the WRITE DATA STROBE WDS The rate of serial WRITE DATA to the Disk is controlled by dividing the Altair 2MHz Clock ENTER NEW WRITE DATA ENWD is the Status signal generated by the Write Circuit when new WRITE OATA is requested When INDEX and SECTOR pulses are received by the Index Sector Circuit the INDEX pulse is detected Sector count beginning with Sector may begin T...

Page 97: ... With All HIGH F5 pin 8 goes LOW and is inverted HIGH to A5 pin 1 zone D6 Address lines A10 A8 when equal to XX0g XXI8 or XX2g XX represents a User Selectable con dition for address lines A11 A15 described above enable one of the AND gates B4 pins 6 8 or 12 zone C6 When A8 A9 and A10 are all LOW B4 pin 6 is enabled allowing an Input or Output on Channel 010g When A9 is HIGH and A10 and A8 are LOW ...

Page 98: ...inverted E5 pin 3 appears HIGH at the Index Window Gate A4 pin 11 zone C5 A4 separates the Index pulse from the Sector pulses A2 pin 10 is enabled HIGH when E5 pin 3 goes LOW Sector Pulse One Shot El pin 13 zone C4 goes HIGH for 3G0ys which triggers Index Window One Shot El pin 5 zone C4 HIGH for 9 6ms A4 pin 8 zone C5 is only enabled when the Index pulse enables E5 pin 3 since El pin 4 zone C4 an...

Page 99: ...o o W Ll o in C V J 1 c o o uo c o CO CM c o o t o L L C V J rr I I 10 i I UJ CO o i 1 r Ts i i J zn ut c o cr CVJ 1 c o o LO o o Jj 11 1 CM 5 uii 5 I _ M C V J UI U i S U S Ti 1 5 C O Q Figure 2 5 Index Sector Timing 248067A 89 ...

Page 100: ...d the delay time of the RC time constant of R8 and C20 A2 pin 1 zone C3 is HIGH for 500ns 250ns if FT pin 12 zone B3 has been triggered LOW This clocks B3 pin 8 zone C3 LOW if B3 pin 7 the HEAD STATUS HS signal is HIGH HEAD STATUS should go HIGH 50ms after the head is loaded on the Disk A LOW at B3 pin 8 indicates that the correct Index pulse has been detected The Index Latch in allowing E2 pin 11...

Page 101: ...ccurs 4ys later if it is a logic 1 refer to Figure 4 6 When a clock pulse is received E5 pin 6 is enabled HIGH triggering Read Clock One Shot A1 pin 4 zone B6 LOW for 2ys This LOW is present at the Read Data Window Gate A4 pin 13 zone B4 A1 pin 13 is HIGH for 2ys triggering the Read Data Window Gate A1 pin 5 zone B4 HIGH and A1 pin 12 LOW for 6 1ys A1 pin 4 returns HIGH after 2ys leaving A4 pin 13...

Page 102: ...er B1 refer to Figure 2 7 counts eight read clocks and toggles on the trailing edge of the Q output at A1 pin 12 zone B4 A2 pin 11 zone D5 goes HIGH every 64ys on the leading edge of the clock pulse at B1 pin 2 G1 pin 13 zone C4 goes HIGH seven read data clocks after the sync bit has been detected and clocks the Sync Bit Detector Flip Flop B2 pin 8 zone C7 LOW B1 pin 15 returns LOW after 8ys allow...

Page 103: ...E line drivers H4 pins 9 3 5 and 7 zone D2 and H3 pins 5 7 3 and 9 zone C2 allow data at outputs Qa through Qq to be transferred to the Altair Data Bus REA0 CATA CLOCK 81 2 8 3 IT COUNT OUTPUT I M I A2 F 2 2 S 2 3 L TRANSFER OATA 3YTE PULSE 8 3 1 3 NO DATA NEW REAO OATA AVAILA8LE FLIP FLOP NRDA LF I i L i n n n r r 64us 500ns 250ns u t i DATA AVAILABLE Figure 2 7 Read Timing At the beginning of ev...

Page 104: ...inver ters G4 pins 2 3 and 4 to the Disk Address Latch J3 pins 2 and 3 As the clock goes HIGH at J3 pins 13 and 4 data is latched into the D and Dg inputs and as the clock returns LOW data present at the D and Dg inputs is transferred to the Q and Q g outputs The address information then enables one of four possible Disk Drives through line drivers K3 pins 5 and 7 zone C2 The Disk Enable Flip Flop...

Page 105: ...SK POWER line stays HIGH at B3 pin 11 zone C4 allowing B3 pin 9 to be triggered B3 pin 12 is triggered LOW for 3ys enabling El pin 11 HIGH refer to Figure 4 9 This leaves F3 pin 13 zone C5 LOW and the Disk Enable Flip Flop A2 is cleared A2 is also cleared when POC POWER ON CLEAR is LOW or by the DISK CONTROL LATCH when Data line D07 is HIGH This allows F3 pin 13 LOW clearing A2 pin 6 When D07 zone...

Page 106: ...in 9 is present at E3 pin 1 zone D7 and provides the WRTEW Write Enable signal to the Drive When E2 pin 9 goes LOW the Counters and Shift Registers H2 A3 and A4 are cleared The WRITE DATA ENABLE signal refer to Figure 4 10 is generated when the Sector Count True One Shot F4 pin 4 Figure 4 14 Sheet 1 zone A7 is enabled LOW for 30ys triggering the Write Clear One Shot F4 pin 5 zone A5 HIGH for 1ms T...

Page 107: ...k Read Write Timing The Parallel to Serial Write Data Shift Register zone D6 must not be clocked during the 1ms delay at J4 pin 2 Clocking is inhibited when CLOCK INHIB Clock Inhibit H2 pin 6 zone D6 is HIGH Since WRT ENABLE at E3 pin 1 zone D8 is initially LOW and WRT Write DATA STROBE at E3 pin 5 zone D7 is initially HIGH E3 pin 3 zone D7 is HIGH Logic 0 bits are written to the Disk Drive during...

Page 108: ...ks H3 and G3 Data present at D through DQ is transferred to Q through Qq when the clock at pin 13 goes LOW Data is then available at PARALLEL DATA IN of Parallel To Serial Write Data Shift Register H2 zone D6 The Write Byte Counter A4 zone D3 counts eight lus clock pulses from the Write Clock Data Window Generator A3 pin 15 zone D4 to the Parallel To Serial Write Data Shift Register H2 pin 15 refe...

Page 109: ...ne D3 When A Q U T and Bqut are HIGH and CqUT is inverted HIGH by G2 pin 6 zone D4 E4 pin 6 zone D3 is enabled LOW F4 pin 1 zone D3 is enabled HIGH insuring F4 pin 13 is LOW refer to Figure 4 11 and 4 12 and the Disk WRT DATA Write Data input is enabled through line driver K3 pin 9 zone D2 The Write Data Windows zone D3 are devel oped halfway between the write clocks which are generated every 8y s...

Page 110: ..._ r L _ r n r i i L W I N D O W C4 6 HE 7 P A R A L L E L T O S E R I A L S H I F T R E G I S T E R C L O C K R I P P L E C A R R Y O U I P U I W R I T E C L O C K A3 15 L O G I C I W R I T E O A T A F4 I 4MS S H I F T O N R I S I N G E W i En Figure 2 12 Write Timing L_T r i n r i p 0 0 o O k ...

Page 111: ...air Data Out Bus to the Disk Drive unit HIGH signals on the Data lines are inverted by G4 and H4 zone C7 and appear as D0O through D07 at Control Signal Decoding Gates HI and J1 zone B7 Before the decoding gates can be enabled the CONTROL DISK STROBE 011g OUT line zone A8 must be enabled LOW 500ns pulse Refer to Figure 2 13 for timing diagrams relating to Disk Control functions discussed in Paragr...

Page 112: ... START O F S E C T O R C L E A R SOS L J S E C T O R I N T E R R U P T E N A B L E P U L S E JI 13 500ns 250ns L F 500ns S E C T O R I N T E R R U P T E N A B L E F F 2 12 S E C T O R I N T E R R U P T DISABLE P U L S E Jl I 84 9 START O F S E C T O R C L E A R 500ns d t LF500ns 250ns E4 I2 S E C T O R I N T E R R U P T L A T C H E3 I1 R E S E T I N T E R R U P T L A T C H INTERRUPT A C K N O W L ...

Page 113: ...he trailing edge of the 3ms Step Pulse causes the Minidisk head to be moved in one track to higher numbered tracks towards the center of the Minidiskette If D01 is HIGH when outputting to Channel 011g LOWs appear at HI pins 8 and 9 zone B7 causing a HIGH pulse at HI pin 10 The trailing edge of this signal triggers A1 pin 1 zone B4 causing a 3us pulse at A1 pin 4 clearing A2 pin 2 With A2 pin 12 LO...

Page 114: ... the START OF SECTOR CLR pulse occurring at the beginning of each Sector When D02 is HIGH at bus pin 88 zone C8 and an output is done to Control Disk Strobe HI pin 4 is enabled HIGH allowing F1 pin 4 LOW El pin 8 is then allowed HIGH and the Disk Disable Timer is reset This command should be issued before every Read or Write operation to insure the 88 MDS continues to be enabled 2 16 Move Head Sta...

Page 115: ...a i s allowed 2 18 Enable Interrupts When Dp goes LOW J1 pin 13 zone B7 is enabled for 500ns applying a clock pulse to Interrupt Enable Flip Flop E2 zone B3 E2 pin 12 is enabled HIGH and present at Interrupt Latch E4 E4 pin 12 zone A3 is normally HIGH in a Reset condition E3 pin 11 zone A3 is normally HIGH and applied to E4 pin 1 when an interrupt is acknow ledged by the computer s Central Process...

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Page 117: ...H E U W M B 248067A 107 108 Blank ...

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Page 119: ...oper connection When using this test program use Drive address 0 and be sure there is a Minidiskette in the Drive Single step the following program Test Address Instruction 1 000 000 076 MVI A 1 000 Drive Address 0 2 323 Output to 3 010 Disk Enable Channel 2 4 333 Input from 5 on Sector Count Channel 3 6 333 Input from 7 010 Status Channel Test 1 Examine address 000 000 and single step five times ...

Page 120: ...ng Data D1 OFF MH OK To Step The Head D2 OFF HS Head Properly Loaded D3 OFF No Function D4 OFF No Function D5 ON if INTE On Front Panel Off D6 Indicates Track 0 OFF if at TRK 0 D7 ON Flickering NRDA Indicates Read Circuit is Detecting Data If the lights do not appear normal the circuit associated with the questionable light may be defective If all lights are on the trouble is probably in the Addre...

Page 121: ...lear Read Circuit at beginning of Sector TP 6 Index Pulse Verification 8 0 11 2ms Occurs every 200 IC Fl 5 ms when Drive is enabled Used to insure proper detection of Index pulse when Drive first enabled TP 7 Sector True 20 40 s Occurs every 12 5ms when Drive IC F4 13 is enabled Used to indicate beginning of Sector TP 8 Write Data Enable 900 1200ys Occurs every 12 5ms IC F4 5 when Drive is enabled...

Page 122: ...mum of 220g is set by the position of the sense switches Write Data con sists of 1st byte 377g D7 1 sync bit 2nd byte data on sense switch 3rd byte 2nd 1 4th byte 2nd 2 n th byte 001 last byte 000 If sense switches are set to 000 program will stop Step Pulse 150 450ys Occurs when step in or out com mand is issued Used to step Minidisk Drive A minimum of 45ms between step pulses Drive stepping occu...

Page 123: ...ut to a terminal Teletype CRT etc The output program is set to out put on Channel 1 To obtain a useful output pattern change the sense switches until a desirable pattern is printed The characters printed will consist of all printable ASCII characters in reversed order as in 987654321 and ZYXWVU This pattern repeats it self and is easily observed for errors 248067A 113 ...

Page 124: ...21 376 22 300 0 sector JNZ 23 302 Jump if not start of 0 sect 24 oi 7 n to WSECT 25 000 J MVI A 26 076 MVI A 27 200 Write enable bit 30 323 31 o n Disk function control channel 32 333 First byte test 33 010 Disk status channel ANA A B 34 240 Test for ENWD status JNZ 35 302 Jump if ENWD false 1 36 0 3 2 1 to FBYT 37 000 J MOV A D 40 172 Move 377 into accum OUT 41 323 Output first byte 42 012 Disk d...

Page 125: ... channel CPI 102 376 Sector position channel 103 300 0 sector JNZ 104 302 Jump if not start of j 3 sect 105 100 to RSECT 106 000 IN 107 333 Start of NRDA test 110 010 Disk status channel ANA A B m 240 Test for NRDA status JNZ 112 302 Jumo if NRDA false 1 113 107 to RDTST 114 000 1 IN 115 333 Input read data 116 012 Disk data channel M O V M H A 117 167 Store data in nremory H L INR L 120 054 Incre...

Page 126: ...D1 0 busy 147 142 Jump if D1 0 busy 150 000 _1 To OTST mov amm 151 176 Move data PROM mem to Accum OUT 152 323 Output data 153 021 To I O port INR L 154 054 Increment L register JNZ 155 302 If L f 0 output another byte jump 156 142 157 000 To OTST MVI A 160 076 161 000 Enable Disk 162 323 163 010 164 303 Jump 165 004 Jump 000 166 000 _1 To LDHD If using the old SIOA board replace instructions from...

Page 127: ... 151 323 152 010 JMP 153 303 tl 54 0 0 4 1 fI55 000 J 156 157 EXPLANATION Test output device for busy Status chan of terminal Test bit 0 rotate into carry Jump if carry b i t 0 1 to OTST Move data from mem H L Output data Data channel for term Increment L register Jump if L reg f 0 output another byte to OTST Enable disk To LDHD For R W step loop change Data at 000 154 to 037 Data at 000 155 to 00...

Page 128: ...248067A ...

Page 129: ...nd step functions simultaneously the two programs may be run together by changing the following 1 Data in locations 000 154 and 000 155 to 037 001 as indicated 2 Data in location 001 034 to 303 as indicated Begin the program at 001 000 the start of the Stepping Program The Disk head will step out to Track 0 The head will then load and a Write Read will occur The head will then unload and output wi...

Page 130: ...2 Bit Dl 1 step out OUT 17 323 Output data 002 to 20 on Disk function control channel DCR E 21 035 Decrement step counter E reg JNZ 22 302 Jump if E reg f 0 23 006 to SOUT 24 001 IN 25 333 Test for track 0 status 26 010 Disk status channel AN I 27 346 Test 30 100 D6 mask JNZ 31 302 Jump if track 0 false D6 l 32 025 to TZ 33 001 J NOP 34 000 NOP 35 000 NOP 36 000 IN 37 333 Test MH status bit move h...

Page 131: ...Add 1 to E register MVI A 53 076 54 042 34 steps CMP A E 55 273 Compare 11 E reg to 34 JNZ 56 302 Jump if E reg f 34 57 034 To Loop 60 001 to Looo JMP 61 303 Jump if E reg 34 62 004 1 to NOS 63 001 J 64 65 66 67 Change to 303 for Step R W loop 248067A 121 ...

Page 132: ...M I N I D I S K S T E P P I N G P R O G R A M F L O W C H A R T 122 248067A ...

Page 133: ...n a n u s 123 124 Blank ...

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Page 135: ... 5 volts In the listing below those signal names accompanied by are ineffective or not used in the Altair 8800b Turnkey computer Number Symbol Name 1 8V 8 volts 2 18V 18 volts 3 XRDY External Ready Function Unregulated input to 5 volt regulators Positive unregulated voltage For special applications pulling this line low causes the processor to enter a wait state and allows the status of the normal...

Page 136: ...mpedance tri state Input to the memory protect flip flop Indicates that the computer is in the process of performing a single step Puts the buffers for the 16 address lines in their high impedance tri state Puts the buffers for the 8 data out lines in their high impedance tri state Processor output signal which appears in response to the HOLD signal indi cates that the data and address buffers wil...

Page 137: ...sor is in the fetch cycle for the first byte of an instruction Indicates that the address bus con tains the address of an output de vice and the data bus will contain the output data when PWR is active Indicates that the address bus con tains the address of an input device Indicates that the data bus will carry memory read data Acknowledges a HALT instruction Inverted output of the 2MHz oscil lato...

Page 138: ...ard currently being addressed Indicates that the RUN STOP flip flop is reset Input that controls the run state of the processor If the line is pulled low the processor will enter a WAIT state until it is released The processor recognizes a request on this line at the end of the current instruction or while halted If the processor is in the HOLD state or the Interrupt Enable flip flop is reset it w...

Page 139: ...C A SAVE OF BYTES IN C MVI A 136 CALCULATE NUMBER OF ZEROS TO WRITE SUB C SUBTRACT THE NUMBER OF DATA BYTES MOV B A NUMBER OF ZEROS 1 CALL SECGET LATENCY MVI A 128 ENABLE WRITE WITHOUT SPECIAL CURRENT OUT 9 CALL WITH B NUMBER OF ZEROS C NUMBER OF DATA BYTES AND H L POINTING AT OUTPUT DATA OHLDSK MVI MVI ORA MOV INX NOTYTD IN ANA JNZ ADD OUT 0 1 A 128 M E A H 8 D NOTYTD E 10 SETUP A MASK READY TO W...

Page 140: ...A I T I N G EI R E E N A B L E I N T E R R U P T S M V I A 8 U N L O A D H E A D O U T 9 SEND C O M M A N D R E T DONE O I S K INPUT R O U T I N E ENTER WITH P O I N T E R O F 1 3 7 B Y T E B U F F E R IN H L A L L R E G S D E S T R O Y E D D S K I M V I R E A D O K IN ORA JM IN M O V INX DCR J N Z C A L L S E C G E T C 1 3 7 8 A R E A D O K 10 M A H C R E A D O K P O I N T TO R I G H T S E C T O ...

Page 141: ... A 8 UNLOAO HEAD OUT 9 SEND COMMAND RET SECGET 01 DISABLE INTERRUPTS SECLP2 IN 9 GET SECTOR INFO RAR FIX UP SECTOR JC SECLP2 IF NOT KEEP WAITING AiNI 15 GET SECTOR CMP E IS IT THE ONE WE WANTED JNZ SECLP2 TRY TO FIND IT RET 133 248067A ...

Page 142: ... Channels and a description of their functions A I O Address for the Minidisk Controller Octal Address Mode Description 010 Output from CPU Enables one of four Drives 010 Input to CPU Indicates status of Drives and Controller 011 Output from CPU Controls Drive operation 011 Input to CPU Indicates Sector position of Diskette 012 Output from CPU Write Data 012 Input to CPU Read Data B Definitions of...

Page 143: ...0 0 1 1 0 2 0 1 3 1 1 2 An input to CPU from Minidisk Controller Address 010 gives the Disk System status when a Drive is enabled When a bit is True it is a logic 0 when False the bit is a logic 1 Also all status bits are logic 1 when there is not a Minidiskette in the Drive The status bits are des cribed as follows D0 ENWD Enter New Write Data when True requests that a byte of data be output to t...

Page 144: ... R W head is positioned at the outermost track This status bit should be used for zeroing the software track counter D7 NRDA New Read Data Available when True indicates the Read Circuit has a byte of data ready to be input from the Read Data Channel 012 NRDA occurs every 64us when reading data and is reset each time a byte of Read Data is input from Channel 012 3 An output from the CPU to Minidisk...

Page 145: ...nabled until turned off by Interrupt Disable or the Controller turned off see section 3 9 for more information D5 INTERRUPT DISABLE Disables the Controllers interrupt circuit Interrupts are also disabled when the Controller is turned off D6 Not used D7 WRITE ENABLE turns the Controller and Drive Write Circuits on WRITE ENABLE is reset at the end of each Sector The WRITE ENABLE sequence should be p...

Page 146: ...m in section 5 4 Program 5 1 4 Sector Position An Input to the CPU from Minidisk Controller address 011 gives the Sector position of the Minidiskette in the selected Minidisk Drive Sector position is determined by the rotational position of the Minidiskette The 88 MDS uses a 16 Sector Mini diskette which has 16 Sector holes and one Index hole These holes are sensed optically and cause pulses to be...

Page 147: ...0 ms after a step command is issued When reading a Sector the Read Circuit is disabled during the first 500us to insure valid detection of the sync byte When writing a Sector the Write Circuit should be enabled as near to the Sector True detection as possible When enabled the Write Circuit will automatically write zeros for the first 1ms of the Sector 5 Write Data An output from the CPU to Minidis...

Page 148: ...multaneously Minidisk interrupts are caused by detection of a Sector pulse when interrupts are enabled The most obvious use of the Sector interrupts would be performing a Sector search for Disk I O The Minidisk Controller would interrupt the Altair computer at the beginning of every Sector or every 12 5ms Only a few microseconds would be used in identifying the Sector count and the Altair computer...

Page 149: ...f Vectored Interrupts are implemented use the highest level priority VI0 To enable interrupts the 8080 CPU must have its interrupts enabled Also if Vectored Interrupts are utilized consult the 88 VI RTC manual Then the Minidisk Controller must have its interrupts enabled CPU Interrupts must be re enabled after every interrupt is serviced if more interrupts are required 248067A 141 142 Blank ...

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