I / O a d d r e s s e s , i n t e r r u p t s e t c .
FT5000 HANDBOOK 6/3
Address
Resource
Device
Notes
03D4h - 03DAh
Color Graphics Controller
03E8h - 03EFh
Serial Port A
03F0h - 03F5h
Diskette Controller
03F6h - 03F7h
Primary IDE - Sec. Diskette
03F8h - 03FFh
Serial Port A (Primary)
0400h - 043Fh
DMA Controller 1, Extended Mode Registers
PIIX4E
04D0h - 04D1h
Interrupt Controllers 1 and 2 Control Register
0678h - 067Ah
Parallel Port (ECP)
0778h - 077Ah
Parallel Port (ECP)
07BCh - 07BEh
Parallel Port (ECP)
0CA0 - CA3h
BMC Registers
0CF8h
PCI CONFIG_ADDRESS Register
Located in 450NX
0CF9h
NBX Turbo and Reset control
PIIX4E
0CFCh
PCI CONFIG_DATA Register
Located in 450NX
46E8h
Video Display Controller
Memory map
Address Range (hex)
Amount
Function
0 to 07FFFFh
640 KB
DOS region, base system memory
0A0000h to 0BFFFFh
128 KB
Video or SMM memory
0C0000h and 0DFFFFh
128 KB
Add-in board BIOS and buffer area
0E0000h to 0FFFFFh
128 KB
System BIOS
0E0000h to 0EFFFFh
2 MB
Extended system BIOS
FC000000h to FFFFFFFFh
64 MB
PCI memory space
Interrupts
The table overleaf recommends the logical interrupt mapping of interrupt sources; it reflects a
typical configuration, but these interrupts can be changed by the user. Use the information to
determine how to program each interrupt.
The actual interrupt map is defined using configuration registers in the PIIX4E and the I/O
controller. I/O Redirection Registers in the I/O APIC are provided for each interrupt signal; the
signals define hardware interrupt signal characteristics for APIC messages sent to local APIC(s).
N
NO
OT
TE
E
To disable either IDE controller and reuse the interrupt:
if you plan to disable either IDE
controller to reuse the interrupt for that controller, you must physically unplug the IDE cable from
the board connector (IDE0) if a cable is present. Simply disabling the drive by configuring the SSU
option does not make the interrupt available.