RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
ADDRESS BUS
MAGIC SPI
to MAGIC
MIDRATE_1
RX_ACQ
RX_EN
TX_KEY
DM_CS
TX_EN
CLK_SELCT
RESET
A1
C1
E2
E1
E3
E4
BKLT_EN
Q907
BACK
LIGHT
BKLT_EN
ALERT_VCC
B
E
C
D
IS
P
L
A
Y
GND
15
V2
13
DP_EN_L
1
RESET
2
14
-5V
DP_EN_L
KEYPAD
KBR0, KBR1, KBR2,
KBC0, KBC1, KBC2
PWR_SW
KBR0, KBR1, KBR2, KBR3, KBR4
KBC0, KBC1, KBC2, KBC3, KBC4
to Display
to Keyboard
V1
SIMPD0
DEEP SLEEP
2
1
P2
from G CAP2
from WhiteCap
LS1_IN
LS2_IN
SIM_TX
SIM_RX
( SDTX ) BDX
( TX_CLK ) BCLKX
from / to MAGIC
BCLKR
( SDFS ) BFSR
( SDRX ) BDR
STBY_DL
CIRCUIT
V1
V2
VREF
V1_SW
U800
WHITE_CAP
SPI
INTERFACE
TIMER
SPI
INTERFACE
H10
P4
K3
L7
PB6
A4
A11
H2, H1, H3. G3, G5
J1, J2, J3, J4, J5
UART
INTERF.
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
E9
E7
F3
B5
SIM
INTER
FACE
CTM
MODULE
DSC
SERIAL
INTER
FACE
DSP
CHARGE
CTM
CPU
B6
B3
B4
D4
A3
F1
V2
V3
C14, F10, G4, H4, K5, P13
A9, A10, C5, K6, K10, M8, M11
B7
HEAD_INT_L
J902
5-12
D0-D7
A0
3
U904
U903
4
-10V
1
( -10V )
P2
R_W
4
INT.
DIV.
V1-V5
C702-C706
U900
G_CAP2
J 600
15 PIN EXT CONN.
CON.
2
1
H6 H7 K9
H9
SENSE
CNTL.
MAN_TEST_AD
DSC_EN_AD
DOWNLINK_AD
BATT_THERM_AD
A1
B2
A2
B3
REAL TIME
CLOCK
Y
9
0
0
A7 B7
3
2
.7
6
8
K
H
z
SPR-
A
L
R
T
O
U
T
ALRT_VCC
REG.
V2
REG.
V3
REG.
VBOOST1
REG.
L901
B+
V_BOOST1
V1
V2
V3
VREF
REG.
VREF
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
1,8V, for WhiteCap
VSIM
REG.
VSIM1
V1
5.0V, for DSC Bus, Negative Voltage Regulator
Internal GCap use only (VSIM1, LS_V1)
3.0 or 5.0V, for SIM Card Circuit
P
A
_
D
R
V
RESET
2.775V,for Magic P1
K6
E18
B10
J5
C6
B5
G9
A6
A10, C10
F7
C7
SENSE
BATT+
EXT_B+
14
1
3
10
5
RS232_TX
RS232_RX
6
7
DSC_EN
13
12
11
UPLINK
DOWNLINK
GND
GND
GND
M
A
G
IC
_
1
3
M
H
z
G
C
L
K
CLK
RESET
SIM_I/O
VSIM1
3
1
2
4
6
LEVEL
EXT_B+
D10
PWR_SW
C8
K7
G6
K10
LS1_IN
LS2_IN
SIM_TX
SIM_RX
H8
J803
SIM
Con.
SHIFT
A5
A6
K2
CHARGE
J504
V2
HEAD_INT_L
ALRT
Q903
J9
CR902
F6
J8
J7
Logic Control
A
U
D
IO
S
P
I
D2
C2
R
T
C
_
B
A
T
T
D6
HEADSET
STBY_DL
G4
C4
G
C
A
P
_
C
L
K
1
3
M
H
z
F5
EXT_B+
SELECT
F10
E8
D9
H3
Audio
Codec
Interface
SPI
INTERFACE
15
GND
G5
ON / OFF
9
BATT_FDBK
MO_ST
4
2
8
RS232_EN
ISENSE
CHRGC
E4
E3
E1
E2
C1
A1
N3
V2
BATT_SER_DATA
N/C
C2
EXT_CHG_EN
R976
R977
4
1-3
5-8
from G CAP2
ALRT_VCC
to Backlight
ON_2
VIB MOTOR
M1
U510
VIB_EN
B+
1
5
4
( WhiteCap )
K1
VIB_EN
C5, B6
A5
MAIN_FET
3
J604
4
GND
1
2
BATT CON.
Q905
BATT_THERM_AD
CHRG_EN
CR903
Q905
B+
Q901
BATT+
EXT_B+
Q900
R913
Q909
Q904
MIDRATE_2
L6
For description of Midrate Charger
see document on:
BATT_FDBK
to J600
from Charger
BATT_THERM_AD
BATT_SER_DATA
H5
1,2,5,6
4
3
4
2
1-3
4
6-8
5
2
4,6
Q902
4
7,8
3
4
2
3
STBY_DL
U702
U701
SRAM
EEPROM
EPROM
V2
SR_VCC
CE0
CE1
CE2
CE3
R_W
D6, E1
B2
A1
G5
A4, E1, F5
D7
F8
C9
E10
D9
B9
RESET
E1
SR_VCC
R_W
B3
B11
B4
DATA BUS
VDDS
VCC_MEMIF
VDD
VCCA
http://gsm-service.fle.css.mot.com/
KEYPAD
DISPLAY
INTERFACE
P1
Backlight
LCD
27
26
T
o
A
n
te
n
n
a
B
o
ar
d
ALERT_VCC
BKLT_EN
KBR3, KBR4
KBC3, KBC4
OPEN
1 - 10
B+
11, 37
N/C
12, 13, 15
17, 19, 21
23, 25, 27
28, 30, 32
34, 35, 36
38, 39, 40
41, 42, 43
44, 45, 47
48, 50, 52
53, 54, 56
58, 60 , 62
64, 66, 69
70, 71, 72
CLK_SELECT
14
MQSPI_CS1
16
BDX
18
BCLKX
20
BCLKR
22
BDR
BFSR
24
26
RX_EN
RX_ACQ
29
33
DM_CS
46
MAGIC 13Mhz
MQSPI_CLK
51
VREF
-5V
TX_EN
55
57
59
TX_KEY
STBY_DL
V1_SW
-10V
V1
61
63
65
67
68
J1
Inter-PCB Connector
G
C
A
P
S
P
I
V100 - BLOCK DIAGRAM - PAGE
2
/2
Summary of Contents for 38C V100
Page 1: ...Level 3 Service Manual Model V100 GSM Technology Product Family 38C Personal Communicator ...
Page 2: ......
Page 73: ...V100 BOARD LAYOUT PAGE 1 2 ...
Page 74: ...V100 BOARD LAYOUT PAGE 2 2 ...
Page 77: ...V100 CONNECTOR SCHEMATICS ...
Page 78: ...V100 DISPLAY SCHEMATICS ...
Page 79: ...V100 FM SCHEMATICS ...
Page 81: ......
Page 83: ......