Motorola 68000, Instruction Set

Page 1: ...Motorola 68000 s Instruction Set ...

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Page 3: ...te of the bit is undefined i e its value cannot be predicted The bit remains unchanged by the execution of the instruction The bit is set or cleared according to the outcome of the instruction Unless an addressing mode is implicit e g NOP RESET RTS etc the legal source and destination addressing modes are specified by their assembly language syntax The following notation is used to describe the 68...

Page 4: ...g modes are data register direct and memory to memory with address register indirect using pre decrementing Application The ABCD instruction is used in chain arithmetic to add together strings of BCD digits Consider the addition of two nine digit numbers Note that the strings are stored so that the least significant digit is at the high address LEA Number1 A0 A0 points at first string LEA Number2 ...

Page 5: ...ination operand addressing modes ADDA Add address Operation destination source destination Syntax ADDA ea An Attributes Size word longword Description Add the source operand to the destination address register and store the result in the destination address register The source is sign extended before it is added to the destination For example if we execute ADDA W D3 A4 where A4 0000010016 and D3 W...

Page 6: ...dd immediate Operation destination literal destination Syntax ADDI data ea Attributes Size byte word longword Description Add immediate data to the destination operand Store the result in the destination operand ADDI can be used to add a literal directly to a memory location For example ADDI W 1234 2000 has the effect M 200016 M 200016 123416 Condition codes X N Z V C Destination operand addressin...

Page 7: ...utomatically if the constant is in the range 1 to 8 Condition codes Z N Z V C Note that the CCR is not updated if the destination operand is an address register Destination operand addressing modes ADDX Add extended Operation destination source destination X Syntax ADDX Dy Dx ADDX Ay Ax Attributes Size byte word longword Description Add the source operand to the destination operand along with the ...

Page 8: ...le precision operations AND AND logical Operation destination source destination Syntax AND ea Dn AND Dn ea Attributes Size byte word longword Description AND the source operand to the destination operand and store the result in the destination location Application AND is used to mask bits If we wish to clear bits 3 to 6 of data register D7 we can execute AND 10000111 D7 Unfortunately the AND oper...

Page 9: ...nd The ANDI permits a literal operand to be ANDed with a destination other than a data register For example ANDI FE00 1234 or ANDI B F0 A2 Condition codes X N Z V C 0 0 Destination operand addressing modes ANDI to CCR AND immediate to condition code register Operation CCR data CCR Syntax ANDI data CCR Attributes Size byte Description AND the immediate data to the condition code register i e the le...

Page 10: ...NDI data SR Attributes Size word Description AND the immediate data to the status register and store the result in the status register All bits of the SR are affected Application This instruction is used to clear the interrupt mask the S bit and the T bit of the SR ANDI data SR affects both the status byte of the SR and the CCR For example ANDI 7FFF SR clears the trace bit of the status register w...

Page 11: ...sign change occurs during shifting i e if the most significant bit changes value during shifting The effect of an arithmetic shift right is to shift the least significant bit into both the X and C bits of the CCR The most significant bit i e the sign bit is replicated to preserve the sign of the number Application ASL multiplies a two s complement number by 2 ASL is almost identical to the corresp...

Page 12: ...ffset A short branch to the next instruction is impossible since the branch code 0 indicates a long branch with a 16 bit offset The assembly language form BCC 8 means branch to the point eight bytes from the current PC if the carry bit is clear BCC branch on carry clear C BCS branch on carry set C BEQ branch on equal Z BGE branch on greater than or equal N V N V BGT branch on greater than N V Z N ...

Page 13: ...s BCC branch on carry clear and BCS branch on carry set can be renamed as BHS branch on higher than or same and BLO branch on less than respectively Many 68000 assemblers support these alternative mnemonics Condition codes X N Z V C BCHG Test a bit and change Operation Z bit number OF destination bit number OF destination bit number OF destination Syntax BCHG Dn ea BCHG data ea Attributes Size byt...

Page 14: ... bit tested is zero cleared otherwise Destination operand addressing modes Note that data register direct i e Dn addressing uses a longword operand while all other modes use a byte operand BCLR Test a bit and clear Operation Z bit number OF destination bit number OF destination 0 Syntax BCLR Dn ea BCLR data ea Attributes Size byte longword Description A bit in the destination operand is tested and...

Page 15: ... addressing uses a longword operand while all other modes use a byte operand BRA Branch always Operation PC PC d Syntax BRA label BRA literal Attributes Size byte word Description Program execution continues at location PC d The displace ment d is a two s complement value 8 bits for a short branch and 16 bits for a long branch The value in the PC corresponds to the current location plus two Note t...

Page 16: ...wing bit manipulation of all bits in a data register If a memory location is the destination a byte is read from that location the bit operation performed using bit number modulo 8 and the byte written back to the location Bit zero refers to the least significant bit The bit number for this operation may be specified either by an immediate value or dynamically by the contents of a data register Co...

Page 17: ...addressing and therefore position independent code its use is preferable to JSR Condition codes X N Z V C BTST Test a bit Operation Z bit number OF destination Syntax BTST Dn ea BTST data ea Attributes Size byte longword Description A bit in the destination operand is tested and the state of the specified bit is reflected in the condition of the Z bit in the CCR The destination is not modified by ...

Page 18: ... upper bound is a two s complement integer If the data register value is less than zero or greater than the upper bound contained in the operand word then the processor initiates exception processing Application The CHK instruction can be used to test the bounds of an array element before it is used By performing this test you can make certain that you do not access an element outside an array Con...

Page 19: ...pecified effective address before the clear i e write operation is executed Under certain circum stances this might cause a problem e g with write only memory Condition codes X N Z V C 0 1 0 0 Source operand addressing modes CMP Compare Operation destination source Syntax CMP ea Dn Sample syntax CMP Test A6 D3 W D2 Attributes Size byte word longword Description Subtract the source operand from the...

Page 20: ...e operand from the destination address register and set the condition codes accordingly The address register is not modified The size of the operation may be specified as word or longword Word length operands are sign extended to 32 bits before the comparison is carried out Condition codes X N Z V C Source operand addressing modes CMPI Compare immediate Operation destination immediate data Syntax ...

Page 21: ...scription Subtract the source operand from the destination operand and set the condition codes accordingly The destination is not modified by this instruction The only permitted addressing mode is address register indirect with post incrementing for both source and destination operands Application Used to compare the contents of two blocks of memory For example Compare two blocks of memory for equ...

Page 22: ...as DBF and DBT F false and T true Note that many assemblers permit the mnemonic DBF to be expressed as DBRA i e decrement and branch back It is important to appreciate that the condition tested by the DBcc instruction works in the opposite sense to a Bcc conditional branch instruction For example BCC means branch on carry clear whereas DBCC means continue i e exit the loop on carry clear That is t...

Page 23: ...and the source is a 16 bit value The result i e destination register is a 32 bit value arranged so that the quotient is the lower order word and the remainder is the upper order word DIVU performs division on unsigned values and DIVS performs division on two s complement values An attempt to divide by zero causes an exception For DIVS the sign of the remainder is always the same as the sign of the...

Page 24: ...on Syntax EOR Dn ea Sample syntax EOR D3 A3 Attributes Size byte word longword Description EOR exclusive or the source operand with the destination operand and store the result in the destination location Note that the source operand must be a data register and that the operation EOR ea Dn is not permitted Application The EOR instruction is used to toggle i e change the state of selected bits in t...

Page 25: ...ration CCR literal CCR Syntax EORI data CCR Attributes Size byte Description EOR the immediate data with the contents of the condition code register i e the least significant byte of the status register Application Used to toggle bits in the CCR For example EORI 0C CCR toggles the N and Z bits of the CCR Condition codes X N Z V C X toggled if bit 4 of data 1 unchanged otherwise N toggled if bit 3 ...

Page 26: ...rwise V toggled if bit 1 of data 1 unchanged otherwise C toggled if bit 0 of data 1 unchanged otherwise EXG Exchange registers Operation Rx Ry Ry Rx Syntax EXG Rx Ry Sample syntax EXG D3 D4 EXG D2 A0 EXG A7 D5 Attributes Size longword Description Exchange the contents of two registers The size of the instruction is a longword because the entire 32 bit contents of two registers are exchanged The in...

Page 27: ...the designated data register is copied to bits 8 15 If the operation is longword sized bit 15 is copied to bits 16 31 Application If D0 12345678 EXT W D0 results in 1234007816 If D0 12345678 EXT L D0 results in 0000567816 Condition codes X N Z V C 0 0 ILLEGAL Illegal instruction Operation SSP SSP 4 M SSP PC SSP SSP 2 M SSP SR PC Illegal instruction vector Syntax ILLEGAL Attributes None Description...

Page 28: ...tes Unsized Description Program execution continues at the effective address specified by the instruction Application Apart from a simple unconditional jump to an address fixed at compile time i e JMP label the JMP instruction is useful for the calculation of dynamic or computed jumps For example the instruction JMP A0 D0 L jumps to the location pointed at by the contents of address register A0 of...

Page 29: ...e operand addressing modes LEA Load effective address Operation An ea Syntax LEA ea An Sample syntax LEA Table A0 LEA Table PC A0 LEA 6 A0 D0 L A6 LEA Table PC D0 A6 Attributes Size longword Description The effective address is computed and loaded into the specified address register For example LEA 6 A0 D0 W A1 calculates the sum of address register A0 plus data register D0 W sign extended to 32 b...

Page 30: ... Source operand addressing modes Condition codes X N Z V C LINK Link and allocate Operation SP SP 4 M SP An An SP SP SP d Syntax LINK An displacement Sample syntax LINK A6 12 Attributes Size word Description The contents of the specified address register are first pushed onto the stack Then the address register is loaded with the updated stack pointer Finally the 16 bit sign extended displacement ...

Page 31: ...N Z V C The LINK instruction does not affect the CCR LSL LSR Logical shift left right Operation destination destination shifted by count Syntax LSL Dx Dy LSR Dx Dy LSL data Dy LSR data Dy LSL ea LSR ea Attributes Size byte word longword Description Logically shift the bits of the operand in the specified direction i e left or right A zero is shifted into the input position and the bit shifted out ...

Page 32: ...ast bit shifted out was a 1 Condition codes X N Z V C 0 The X bit is set to the last bit shifted out of the operand and is equal to the C bit However a zero shift count leaves the X bit unaffected and the C bit cleared Destination operand addressing modes MOVE Copy data from source to destination Operation destination source Syntax MOVE ea e Sample syntax MOVE A5 A2 MOVE A5 A2 MOVE 123 A6 MOVE Tem...

Page 33: ...addressing modes Destination operand addressing modes MOVEA Move address Operation An source Syntax MOVEA ea An Attributes Size word longword Description Move the contents of the source to the destination location The destination is an address register The source must be a word or longword If it is a word it is sign extended to a longword The condition codes are not affected Application The MOVEA ...

Page 34: ...ates LEA Ai An An Ai MOVEA Ai An An M Ai Condition codes X N Z V C Source operand addressing modes MOVE to CCR Copy data to CCR from source Operation CCR source Syntax MOVE ea CCR Attributes Size word Description Move the contents of the source operand to the condition code register The source operand is a word but only the low order byte contains the condition codes The upper byte is neglected No...

Page 35: ...ion location The source operand the status register is a word This instruction is not privileged in the 68000 but is privileged in the 68010 68020 and 68030 Executing a MOVE SR ea while in the user mode on these processors results in a privilege violation trap Condition codes X N Z V C Destination operand addressing modes MOVE to SR Copy data to SR from source Operation IF S 1 THEN SR source ELSE ...

Page 36: ...bits of the CCR sets the S bit clears the T bit and sets the interrupt mask level to 7 Condition codes X N Z V C Source operand addressing modes MOVE USP Copy data to or from USP Operation 1 IF S 1 MOVE USP An form THEN USP An ELSE TRAP Operation 2 IF S 1 MOVE An USP form THEN An USP ELSE TRAP Syntax 1 MOVE USP An Syntax 2 MOVE An USP Attributes Size longword Description Move the contents of the u...

Page 37: ...en if the destination is a data register When a group of registers is transferred to or from memory using an addressing mode other than pre decrementing or post incrementing the registers are transferred starting at the specified address and up through higher addresses The order of transfer of registers is data register D0 to D7 followed by address register A0 to A7 For example MOVEM L D0 D2 D4 A5...

Page 38: ...struction has a side effect An extra bus cycle occurs for memory operands and an operand at one address higher than the last register in the list is accessed This extra access is an overshoot and has no effect as far as the programmer is concerned However it could cause a problem if the overshoot extended beyond the bounds of physical memory Once again remember that MOVEM W sign extends words when...

Page 39: ...in conjunction with 8 bit peripherals connected to the 68000 s 16 bit data bus The high order byte of the data register is transferred first and the low order byte transferred last The memory address is specified by the address register indirect mode with a 16 bit offset If the address is even all transfers are to or from the high order half of the data bus If the address is odd all the transfers ...

Page 40: ...data is an eight bit field within the MOVEQ op code and specifies a signed value in the range 128 to 127 When the source operand is transferred it is sign extended to 32 bits Consequently although only 8 bits are moved the MOVEQ instruction is a longword operation Application MOVEQ is used to load small integers into a data register Beware of its sign extension The two operations MOVE B 12 D0 and ...

Page 41: ... the destination result is a 32 bit longword The product is therefore a correct product and is not truncated MULU performs multiplication with unsigned values and MULS performs multiplication with two s complement values Application MULU D1 D2 multiplies the low order words of data registers D1 and D2 and puts the 32 bit result in D2 MULU 1234 D3 multi plies the low order word of D3 by the 16 bit ...

Page 42: ...it is set if a decimal borrow occurs The X bit is set to the same value as the C bit Destination operand addressing modes NEG Negate Operation destination 0 destination Syntax NEG ea Attributes Size byte word longword Description Subtract the destination operand from 0 and store the result in the destination location The difference between NOT and NEG instructions is that NOT performs a bit by bit...

Page 43: ...e as NEG except that the X bit is also subtracted from zero Condition codes X N Z V C The Z bit is cleared if the result is non zero and is unchanged otherwise The X bit is set to the same value as the C bit Destination operand addressing modes NOP No operation Operation None Syntax NOP Attributes Unsized Description The no operation instruction NOP performs no computation Execution continues with...

Page 44: ... destination Syntax NOT ea Attributes Size byte word longword Description Calculate the logical complement of the destination and store the result in the destination The difference between NOT and NEG is that NOT performs a bit by bit logical complementation while a NEG performs a two s complement arithmetic subtraction More over NEG updates all bits of the CCR while NOT clears the V and C bits up...

Page 45: ...R L F0000000 D0 Condition codes X N Z V C 0 0 Source operand addressing modes Destination operand addressing modes ORI OR immediate Operation destination literal destination Syntax ORI data ea Attributes Size byte word longword Description OR the immediate data with the destination operand Store the result in the destination operand Condition codes X N Z V C 0 0 Application ORI forms the logical O...

Page 46: ...CCR Condition codes X N Z V C X is set if bit 4 of data 1 unchanged otherwise N is set if bit 3 of data 1 unchanged otherwise Z is set if bit 2 of data 1 unchanged otherwise V is set if bit 1 of data 1 unchanged otherwise C is set if bit 0 of data 1 unchanged otherwise ORI to SR Inclusive OR immediate to status register Operation IF S 1 THEN SR literal SR ELSE TRAP Syntax ORI data SR Attributes Si...

Page 47: ... PEA and LEA is that LEA calculates an effective address and puts it in an address register while PEA calculates an effective address in the same way but pushes it on the stack Application PEA calculates an effective address to be used later in address register indirect addressing In particular it facilitates the writing of position independent code For example PEA TABLE PC calculates the address ...

Page 48: ...uction is used to perform a programmed reset of all peripherals connected to the 68000 s RESET pin Condition codes X N Z V C ROL ROR Rotate left right without extend Operation destination destination rotated by count Syntax ROL Dx Dy ROR Dx Dy ROL data Dy ROR data Dy ROL ea ROR ea Attributes Size byte word longword Description Rotate the bits of the operand in the direction indicated The extend bi...

Page 49: ...the value is modulo 64 allowing a range of 0 to 63 If no count is specified the word at the effective address is rotated by one place e g ROL ea Condition codes X N Z V C 0 The X bit is not affected and the C bit is set to the last bit rotated out of the operand C is set to zero if the shift count is 0 Destination operand addressing modes ROXL ROXR Rotate left right with extend Operation destinati...

Page 50: ...ll as the X bit The shift count may be specified in one of three ways the count may be a literal the contents of a data register or the value 1 An immediate count permits a shift of 1 to 8 places If the count is in a register the value is modulo 64 and the range is from 0 to 63 If no count is specified the word at the specified effective address is rotated by one place i e ROXL ea Condition codes ...

Page 51: ...Condition codes X N Z V C The CCR is restored to its pre exception state RTR Return and restore condition codes Operation CCR M SP SP SP 2 PC M SP SP SP 4 Syntax RTR Attributes Unsized Description The condition code and program counter are pulled from the stack The previous condition code and program counter are lost The supervisor portion of the status register is not affected Application If you ...

Page 52: ...e byte Description Subtract the source operand from the destination operand together with the X bit and store the result in the destination Subtraction is performed using BCD arithmetic The only legal addressing modes are data register direct and memory to memory with address register indirect using auto decrementing Condition codes X N Z V C U U Z Cleared if result is non zero Unchanged otherwise...

Page 53: ... SGT set on greater than N V Z N V Z SHI set on higher than C Z SLE set on less than or equal Z N V N V SLS set on lower than or same C Z SLT set on less than N V N V SMI set on minus i e negative N SNE set on not equal Z SPL set on plus i e positive N SVC set on overflow clear V SVS set on overflow set V SF set on false i e set never 0 ST set on true i e set always 1 Condition codes X N Z V C Des...

Page 54: ...ed If an interrupt request arrives whose priority is higher than the current processor priority an interrupt exception occurs otherwise the interrupt request has no effect If the bit of the immediate data corresponding to the S bit is clear i e user mode selected execution of the STOP instruction will cause a privilege violation An external reset will always initiate reset exception processing Con...

Page 55: ...rand and store the result in the destination address register Word operations are sign extended to 32 bits prior to subtraction Condition codes X N Z V C Source operand addressing modes SUBI Subtract immediate Operation destination destination literal Syntax SUBI data ea Attributes Size byte word longword Description Subtract the immediate data from the destination operand Store the result in the ...

Page 56: ... to 8 Word and longword operations on address registers do not affect condition codes A word operation on an address register affects the entire 32 bit address Condition codes X N Z V C Destination operand addressing modes SUBX Subtract extended Operation destination destination source X Syntax SUBX Dx Dy SUBX Ax Ay Attributes Size byte word longword Description Subtract the source operand from th...

Page 57: ... SWAP Dn instruction enables the higher order word in a register to take part in word operations by moving it into the lower order position SWAP Dn is effectively equivalent to ROR L Di Dn where Di 16 However SWAP clears the C bit of the CCR whereas ROR sets it according to the last bit to be shifted into the carry bit Condition codes X N Z V C 0 0 The N bit is set if most significant bit of the 3...

Page 58: ...the resource if it was free Because the operation is indivisible no other processor can access the memory between the testing of the bit and its subsequent setting Condition codes X N Z V C 0 0 Source operand addressing modes TRAP Trap Operation S 1 SSP SSP 4 M SSP PC SSP SSP 2 M SSP SR PC vector Syntax TRAP vector Attributes Unsized Description This instruction forces the processor to initiate ex...

Page 59: ...he CCR is set then initiate exception processing The exception vector is located at address 01C16 This instruction is used in arithmetic operations to call the operating system if overflow occurs Condition codes X N Z V C TST Test an operand Operation CCR tested operand i e operand 0 update CCR Syntax TST ea Attributes Size byte word longword Description The operand is compared with zero No result...

Page 60: ...dress register and the old contents of the stack pointer are lost this has the effect of collapsing the stack frame The address register is then loaded with the longword pulled off the stack Application The UNLK instruction is used in conjunction with the LINK instruction The LINK creates a stack frame at the start of a procedure and the UNLK collapses the stack frame prior to a return from the pr...