HC05A24EM USER’S MANUAL
MOTOROLA
3-4
3
3.2
EVS LIMITATIONS
This paragraph explains the limitations that apply to using your A24EM
in an HC05EVS.
•
Limitation 1. CLI/RTI:
You may not trace a clear interrupt mask (CLI) or return from interrupt
(RTI) instruction with an interrupt enabled and pending, due to MCU
interrupt handling. Attempting such a trace causes an interrupt in the
monitor map; this forces a software reset of the HC05EVS. User break-
points remain in the user map as SWI instructions; You must remove
such SWI instructions.
•
Limitation 2. Branch:
Do not trace a conditional branch instruction (such as BRCLR) that
branches to itself. As the monitor places an SWI instruction on the
object of the branch, the system never would execute the instruction.
However, it would appear to you that the instruction had executed. You
may enter a G command while the PC points to this type of instruction
as long as the instruction is not a breakpoint address.
•
Limitation 3. IRQ/SWI:
Whenever possible, avoid mixing interrupt requests (IRQs) and user
software interrupts (SWIs). This prevents a possible IRQ-SWI timing
problem: a concurrent hardware interrupt and SWI could cause an
HC05EVS failure that could stop program execution. To recover from
such a failure (which occurs very infrequently, statistically), press the
master reset switch (SW3).
•
Limitation 4. Memory Map:
You must be aware of the memory map of the MCU being simulated; be
sure to use only valid ROM locations. The HC05EVS does not provide
protection to limit user programs to the exact amount of MCU ROM
available. (For information about memory maps, consult the technical
data book for the MCU.)
