6881094C31-E
November 16, 2006
: VOCON Board
3-31
3.2.4.1.6 13 MHz Reference Generation for GCAP II
The 13 MHz reference is required by the GCAP II IC for the CODEC time base and the SSI clock
generator module internal to the Flipper IC. A phase locked loop (PLL) is used to generate the
13 MHz using the 16.8 MHz clock, which is provided to the Flipper IC REF_16_IN pin (C307). An
external RC loop filter network, consisting of R301, C301, and C302, is connected to the PLL_LFT
pin.
The 13 MHz reference output pin, REF_13_OUT, is conditioned by the RC network of R302 and
C303. The signal at REF_13_OUT is a 3-V peak-to-peak square wave, and the RC filter produces a
lower-level triangle wave that is suitable for the GCAP II IC.
The 13 MHz reference is disabled as the Flipper IC powers up. The 13 MHz reference is enabled by
the Patriot IC through the SPI bus, and, during normal radio operation, this signal should be present.
3.2.4.1.7 SSI Clock and Frame Sync Generator
The Flipper IC generates the SSI clock and frame sync signals for the SAP bus used by the Patriot
IC, GCAP II IC, and encryption module. These signals are generated from the 13 MHz reference.
The SSI clock output pin is labeled SSI_CLK, and the frequency is 520 kHz. The SSI frame sync
output pin is FRSYNC, and the frequency is 8 kHz. These signals are not active when the Flipper IC
comes out of reset, so they are programmed by the Patriot IC through the SPI bus.
The Flipper IC provides four 16-bit TDM slots per frame on the SAP bus. The first slot (slot 0) begins
immediately after the frame sync pulse, and this slot is used by the GCAP II IC. The SEC_SS_X pin
is active for the first 8 bits of the second slot (slot 1). This signal is used by the encryption module to
synchronize its input and output to the SSI frame. The other two slots are reserved for possible
design additions in the future.
On the NNTN4717 VOCON board, the Flipper IC is not programmed to generate the SSI clock, SSI
frame sync signal, or the secure slave select signal (SEC_SS_X); the dual-core processor U401
generates these signals.
3.2.4.2 MAKO IC U501 (for NNTN5567)
The digital-support functions are performed by the MAKO IC. The MAKO IC is contained in a 176-
pin BGA with 0.8mm pitch solder balls. The MAKO IC is supplied with three clocks. It is supplied with
a 16.8 MHz clock from the transceiver board. It uses a 32.768 kHz crystal to boot up the dualcore
processor and for the real-time clock. It also uses a 24.576 MHz crystal to generate the SAP clock
and frame synchronization signals.
The MAKO IC includes that one-wire option detect support, watchdog timer, and the radio's universal
(accessory) side connector interface. It also monitors the position of the on/off switch in order to
control the power-up/power-down sequence.
3.2.4.2.1 Side Connector Interface, Logic Level Translation, and Boot Data Path Control
For kit NNTN5567A the LH Data bidirectional translation is performed internal to the Mako IC and 3V
logic level is on Mako pin SB96D_BDO_KF_3V.
3.2.4.2.2 USB Transceiver
In kit NNTN5567A, the USB transceiver is internal to MAKO IC U501, and is capable of transmitting
and receiving serial data at a rate of 12 megabits per second. The differential USB data comes from
the side connector, through the 27-ohm resistors R252 and R253 and then to the USB1_DP and
USB1_DM pins on U501. The data will then go through some interfacing and multiplexing internal to
the transceiver for 6-wire USB operation and onto the output pins. The USB receive interface
through the transceiver to the dual core processor is as follows: DP routed to USB_VPI, DM routed
to URXD1_USB_VMI, and the differentially decoded data is output on URTS1_XRXD pin.
Summary of Contents for ASTRO XTS-5000
Page 7: ...vi Table of Contents November 16 2006 6881094C31 E Notes ...
Page 11: ...x List of Figures November 16 2006 6881094C31 E Notes ...
Page 17: ...November 16 2006 6881094C31 E xvi CommercialWarranty Notes ...
Page 31: ...November 16 2006 6881094C31 E xxx Portable Radio Model Numbering System Notes ...
Page 83: ...November 16 2006 6881094C31 E 3 44 Theory of Operation Encryption Module ...
Page 135: ...November 16 2006 6881094C31 E 5 44 Troubleshooting Charts Secure Hardware Failure Notes ...
Page 175: ...November 16 2006 6881094C31 E 7 32 Troubleshooting Tables List of Board and IC Signals Notes ...
Page 367: ...November 16 2006 6881094C31 E Glossary 10 Notes ...
Page 373: ...Index 6 November 16 2006 6881094C31 E Notes ...