Motorola ASTRO XTSTM 4000 Detailed Service Manual Download

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6871620L01-C

May 28, 2008

VOCON Section

3-17

General-Purpose Input/Output (GPIO) Module

The General-Purpose Input/Output (GPIO) module is shared by the MCU and the DSP. This module
consists of four 16-pin bi-directional ports and a 15 pin bi-directional port. While some of the pins on
these ports are being used for other functions (UART, SPI, SAP, BBP, and Interrupt pins), the
remaining pins can be programmed to become GPIOs that can be used by either the DSP or the
MCU. Each GPIO pin has up to 8 alternate output functions and up to 4 alternate input functions.
This allows for the GPIO pins to be routed internally to pertinent Patriot IC modules. Additionally, the
GPIO module adds selectable edge-triggered or level-sensitive interrupt functionality to the GPIO
pins. Some examples of GPIO pins include the Display module backlight brightness control signals
(DISP_BRIGHT1 and DISP_BRIGHT2), the Keypad backlight enable signal (KP_BLEN) and the Flip
Assembly Open/Close Sense Signal (FLIP_SENSE).

3.2.2.2 Static RAM (SRAM) U1409

The static RAM (SRAM) IC U1409 is an asynchronous, 4 MB, CMOS device that is capable of 70 ns
access speed. It is supplied with 1.875 volts. The SRAM has its 19 address lines and 16 data lines
connected to the EIM of the Patriot IC through the Address(23:0) and Data(15:0) busses.

The SRAM has an active-high chip select CE2 that is tied directly to the 1.875 V supply and an
active-low chip select EN_CE that is connected to the EIM CS2_N pin. When the SRAM EN_CE pin
is not asserted, the SRAM is in standby mode, which reduces current consumption.

Two other control signals from the EIM that change the mode of the SRAM are the read/write signal,
R/W, and the output enable signal, OE. The R/W of the EIM is connected to the SRAM EN_WE pin,
while the OE signal from the EIM is connected to the SRAM EN_OE pin. The SRAM is in read mode
when the EN_WE pin is not asserted and the EN_OE pin is asserted. The SRAM is in write mode
when the EN_WE pin is asserted, regardless of the state of the EN_OE pin.

The other SRAM pins are the lower-byte enable pin EN_BLE and the upper-byte enable pin
EN_BHE. These pins are used to determine which byte (BLE controls data lines 0-7 and BHE
controls data lines 8-15) is being used when there is a read or a write request from the Patriot IC.
The EN_BLE pin is controlled by the EIM EB1_N signal, while the EN_BHE pin is controlled by the
EB0_N signal.

3.2.2.3 FLASH Memory U1410

The Flash memory IC is an 8 MB CMOS device with simultaneous read/write or simultaneous read/
erase operation capabilities with 70 ns access speed. It is supplied with 1.875 volts. The Flash
memory has its 23 address lines and 16 data lines connected to the EIM of the Patriot IC through the
Address(23:0) and Data(15:0) busses. The Flash memory contains host firmware, DSP firmware,
codeplug data and the transceiver section's tuning values. The Flash memory IC is not field
repairable.

The RESET_OUT of the Patriot IC is at a GPIO voltage logic level. Components D1401 and R1437
are used to convert the voltage down to a 1.875 V logic level, and this 1.875 V reset signal is fed to
the Flash RESET pin. When this pin is asserted (active low logic), the Flash is in reset mode. In this
mode, the internal circuitry powers down, and the outputs become high-impedance connections.

The Flash active-low chip select pin, EN_CE, is connected to the active-low CS0_N pin (CS0 test
point) of the EIM. When the EN_CE is not asserted, the Flash is in standby mode, which reduces
current consumption.