MOTOROLA CMOS LOGIC DATA
MC14555B MC14556B
6–422
Dual Binaryto 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with complementary
MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer
has two select inputs (A and B), an active low Enable input (E), and four
mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the
selected output go to the “high” state, and the MC14556B has the selected
output go to the “low” state. Expanded decoding such as binary–to–hexade-
cimal (1–of–16), etc., can be achieved by using other MC14555B or
MC14556B devices.
Applications include code conversion, address decoding, memory selec-
tion control, and demultiplexing (using the Enable input as a data input) in
digital data transmission systems.
•
Diode Protection on All Inputs
•
Active High or Active Low Outputs
•
Expandable
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
All Outputs Buffered
•
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
±
10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_
C
TL
Lead Temperature (8–Second Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65
_
C To 125
_
C Ceramic
“L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
BLOCK DIAGRAM
2
4
MC14555B
MC14556B
3
1
14
13
15
5
6
7
12
11
10
9
2
4
3
1
14
13
15
5
6
7
12
11
10
9
VDD = PIN 16
VSS = PIN 8
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q0
Q1
Q2
Q3
A
B
E
Q0
Q1
Q2
Q3
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14555B
MC14556B
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
Plastic
MC14XXXBCL
Ceramic
MC14XXXBD
SOIC
TA = – 55
°
to 125
°
C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
v
(Vin or Vout)
v
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
TRUTH TABLE
Inputs
Outputs
Enable Select
MC14555B
MC14556B
E
B
A
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
X = Don’t Care
Summary of Contents for CMOS Logic
Page 1: ......
Page 5: ...iv MOTOROLA CMOS LOGIC DATA ...
Page 6: ...Master Index 1 ...
Page 12: ...Product Selection Guide 2 ...
Page 17: ...The Better Program 3 ...
Page 20: ...B and UB Series Family Data 4 ...
Page 25: ...CMOS Handling and Design Guidelines 5 ...
Page 32: ...CMOS Handling and Design Guidelines 5 ...
Page 39: ...Data Sheets 6 ...
Page 234: ...MOTOROLA CMOS LOGIC DATA MC14174B 6 196 FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM ...
Page 238: ...MOTOROLA CMOS LOGIC DATA MC14175B 6 200 FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM ...
Page 555: ...CMOS Reliability 7 ...
Page 561: ...Equivalent Gate Count 8 ...
Page 563: ...Packaging Information Including Surface Mounts 9 ...
Page 571: ......
