Intel 21555 Non Transparent PCI-to-PCI Bridge
http://www.motorola.com/computer/literature
4-3
4
and address translation between the two processor domains. It accepts a
Type 0 configuration header with configuration space accessible from both
primary and secondary busses. Refer to the CPIP5365 CompactPCI Single
Board Computer Programmer’s Reference Guide for additional
information and programming details.
Intel 21555 Non Transparent PCI-to-PCI Bridge
This nontransparent PCI-to-PCI bridge provides the technology for high
performance embedded and intelligent I/O applications. The Intel 21555 is
designed specifically for applications where a processor is used behind a
PCI-to-PCI bridge. It offers independent address spaces and asynchronous
clocks to deliver application flexibility and allows the local processor to
have complete PCI configuration control of subsystem devices, without
host interference. The CPN5365 allows several options for configuring the
Intel 21555 using the BIOS. For more information, refer to the CPN5365
Single Board Computer Programmer’s Reference Guide listed in
Appendix C, Related Documentation
.
CPN5365 in a Nonhost Slot
The CPN5365 is intended for mounting in a nonhost slot as a peripheral
CPU. The module configures itself for peripheral mode when it plugs into
a peripheral slot. The CompactPCI interface device is a nontransparent
bridge (Intel 21555). The local CPU enumerates the local devices and sets
up the bridge for configuration by the host CPU. The peripheral CPU can
also configure itself onto the Compact PCI bus using a scheme allowing it
to map itself to a particular area using the geographical addressing CPCI
lines.You can read these lines through the FPGA. Refer to the FPGA
register description in the CPN5365 Single Board Computer
Programmer’s Reference Guide for information about reading these bits.
