4-6
Computer Group Literature Center Web Site
Functional Description
4
Field Programmable Gate Array Registers
Use the system’s Field Programmable Gate Array (FPGA) for add-on
features and control, and to connect to the internal ISA bus. The FPGA
consists of a group of I/O registers for control of features such as a
Watchdog Timer, I/O switching control, NVRAM control and decoding,
and system management functions. For registers and programming
information, refer to the CPN5365 Single Board Computer Programmer’s
Reference Guide.
Watchdog Timer
The Field Programmable Gate Array (FPGA) includes a watchdog timer.
The watchdog timer has these modes of operation:
❏
Disabled
❏
Sets the timeout flag in the Watchdog Strobe/Status port in ISA I/O
memory map
❏
Sets the timeout flag in the Watchdog Strobe/Status port in ISA I/O
memory map + Assert a selectable interrupt (ISA IRQ)
❏
Sets the timeout flag in the Watchdog Strobe/Status port in ISA I/O
memory map + Assert NMI followed by a system Reset or Soft
Reset
You can program the watchdog timer using registers in the ISA I/O
memory map. Refer to the CPIP5365 Single Board Computer
Programmer’s Reference Guide for more information about the watchdog
timer and the watchdog timer register.
