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Motorola CPU12, Refrence Manual

The Motorola CPU12, an advanced microprocessor, is designed for various embedded control applications. To gain comprehensive insights and operational instructions, users can access the free Reference Manual. Download it effortlessly from our website and discover the full potential of this highly efficient Motorola CPU12 for your projects.

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CPU12

INSTRUCTION GLOSSARY

MOTOROLA

REFERENCE MANUAL

6-7

U — Unstack 16-bit data. These cycles are extended to two bus cycles if the MCU is

operating with an 8-bit external data bus and the SP is pointing to external mem-
ory. There can be additional stretching when the address space is assigned to
a chip-select circuit programmed for slow memory. These cycles are also
stretched if they correspond to misaligned accesses to a memory that is not de-
signed for single-cycle misaligned access. The internal RAM is designed to al-
low single-cycle misaligned word access.

V — Vector fetch. Vectors are always aligned 16-bit words. These cycles are extend-

ed to two bus cycles if the MCU is operating with an 8-bit external data bus and
the program is stored in external memory. There can be additional stretching
when the address space is assigned to a chip-select circuit programmed for
slow memory.

t — 8-bit conditional read. These cycles are either data read cycles or free cycles,

depending upon the data and flow of the REVW instruction. These cycles are
only stretched when controlled by a chip-select circuit programmed for slow
memory.

T — 16-bit conditional read. These cycles are either data read cycles or free cycles,

depending upon the data and flow of the REV or REVW instruction. These cy-
cles are extended to two bus cycles if the MCU is operating with an 8-bit external
data bus and the corresponding data is stored in external memory. There can
be additional stretching when the address space is assigned to a chip-select cir-
cuit programmed for slow memory. These cycles are also stretched if they cor-
respond to misaligned accesses to a memory that is not designed for single-
cycle misaligned access.

x — 8-bit conditional write. These cycles are either data write cycles or free cycles,

depending upon the data and flow of the REV or REVW instruction. These cy-
cles are only stretched when controlled by a chip-select circuit programmed for
slow memory.

Special Notation for Branch Taken/Not Taken Cases

PPP/P — Short branches require three cycles if taken, one cycle if not taken. Since the

instruction consists of a single word containing both an opcode and an 8-bit off-
set, the not-taken case is simple — the queue advances, another program word
fetch is made, and execution continues with the next instruction. The taken case
requires that the queue be refilled so that execution can continue at a new ad-
dress. First, the effective address of the destination is determined, then the CPU
performs three program word fetches from that address.

OPPP/OPO — Long branches require four cycles if taken, three cycles if not taken. Optional cy-

cles are required because all long branches are page two opcodes, and thus
include the $18 prebyte. The CPU12 treats the prebyte as a special 1-byte in-
struction. If the prebyte is misaligned, the optional cycle is used to perform a pro-
gram word access; if the prebyte is aligned, the optional cycle is used to perform
a free cycle. As a result, both the taken and not-taken cases use one optional
cycle for the prebyte. In the not-taken case, the queue must advance so that ex-
ecution can continue with the next instruction, and another optional cycle is re-
quired to maintain the queue. The taken case requires that the queue be refilled
so that execution can continue at a new address. First, the effective address of
the destination is determined, then the CPU performs three program word fetch-
es from that address.

Summary of Contents for CPU12

Page 1: ...Order this document by CPU12RM AD Rev 1 0 N O N D I S C L O S U R E A G R E E M E N T R E Q U I R E D CPU12 Reference Manual HC12 HC12 HC12 ...

Page 2: ...e body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and d...

Page 3: ...tive Addressing Mode 3 4 3 8 Indexed Addressing Modes 3 5 3 9 Instructions Using Multiple Modes 3 10 3 10 Addressing More than 64 Kbytes 3 12 SECTION 4 INSTRUCTION QUEUE 4 1 Queue Description 4 1 4 2 Data Movement in the Queue 4 2 4 3 Changes in Execution Flow 4 2 SECTION 5 INSTRUCTION SET OVERVIEW 5 1 Instruction Set Description 5 1 5 2 Load and Store Instructions 5 1 5 3 Transfer and Exchange In...

Page 4: ...nd Index Calculation Instructions 5 20 5 25 Condition Code Instructions 5 21 5 26 STOP and WAIT Instructions 5 21 5 27 Background Mode and Null Operations 5 22 SECTION 6 INSTRUCTION GLOSSARY 6 1 Glossary Information 6 1 6 2 Condition Code Changes 6 2 6 3 Object Code Notation 6 2 6 4 Source Forms 6 3 6 5 Cycle by Cycle Execution 6 5 6 6 Glossary 6 8 SECTION 7 EXCEPTION PROCESSING 7 1 Types of Excep...

Page 5: ...0 4 Overlay Window Controls 10 4 10 5 Using Chip Select Circuits 10 5 10 6 System Notes 10 7 APPENDIX A INSTRUCTION REFERENCE A 1 Instruction Set Summary A 1 A 2 Opcode Map A 1 A 3 Indexed Addressing Postbyte Encoding A 1 A 4 Transfer and Exchange Postbyte Encoding A 1 A 5 Loop Primitive Postbyte Encoding A 1 APPENDIX B M68HC11 TO M68HC12 UPGRADE PATH B 1 CPU12 Design Goals B 1 B 2 Source Code Com...

Page 6: ...e TABLE OF CONTENTS C 4 Higher Math Functions C 3 C 5 Conditional If Constructs C 4 C 6 Case and Switch Statements C 4 C 7 Pointers C 4 C 8 Function Calls C 4 C 9 Instruction Set Orthogonality C 5 APPENDIX D ASSEMBLY LISTING INDEX SUMMARY OF CHANGES ...

Page 7: ...Logic 0 8 9 8 5 Tag Input Timing 8 13 9 1 Block Diagram of a Fuzzy Logic System 9 3 9 2 Fuzzification Using Membership Functions 9 4 9 3 Fuzzy Inference Engine 9 8 9 4 Defining a Normal Membership Function 9 10 9 5 MEM Instruction Flow Diagram 9 11 9 6 Abnormal Membership Function Case 1 9 12 9 7 Abnormal Membership Function Case 2 9 13 9 8 Abnormal Membership Function Case 3 9 13 9 9 REV Instruct...

Page 8: ...MOTOROLA CPU12 viii REFERENCE MANUAL ...

Page 9: ...structions 5 12 5 16 Table Interpolation Instructions 5 12 5 17 Short Branch Instructions 5 14 5 18 Long Branch Instructions 5 15 5 19 Bit Condition Branch Instructions 5 16 5 20 Loop Primitive Instructions 5 16 5 21 Jump and Subroutine Instructions 5 17 5 22 Interrupt Instructions 5 18 5 23 Index Manipulation Instructions 5 19 5 24 Stacking Instructions 5 20 5 25 Pointer and Index Calculation Ins...

Page 10: ... Transfer and Exchange Postbyte Encoding A 24 A 6 Loop Primitive Postbyte Encoding lb A 25 B 1 Translated M68HC11 Mnemonics B 2 B 2 Instructions with Smaller Object Code B 3 B 3 Comparison of Math Instruction Speeds B 10 B 4 New M68HC12 Instructions B 11 ...

Page 11: ...e addressing modes found in other Motorola MCUs the CPU12 offers an extensive set of indexed addressing capabilities including Using the stack pointer as an index register in all indexed operations Using the program counter as an index register in all but auto inc dec mode Accumulator offsets allowed using A B or D accumulators Automatic pre or post increment or pre or post decrement by 8 to 8 5 b...

Page 12: ...w status bit C Carry Borrow status bit M 8 bit memory location pointed to by the effective address of the in struction M M 1 16 bit memory location Consists of the location pointed to by the effective address concatenated with the next higher memory loca tion The most significant byte is at location M M M 3 M Y M Y 3 32 bit memory location Consists of the effective address of the instruction conca...

Page 13: ...nges from logic level one to logic level zero ADDR is the mnemonic for address bus DATA is the mnemonic for data bus LSB means least significant bit or bits MSB most significant bit or bits LSW means least significant word or words MSW most significant word or words A specific mnemonic within a range is referred to by mnemonic and number A7 is bit 7 of accumulator A A range of mnemonics is referre...

Page 14: ...MOTOROLA INTRODUCTION CPU12 1 4 REFERENCE MANUAL ...

Page 15: ...ructions It also has two index registers X and Y a 16 bit stack pointer SP a 16 bit program counter PC and an 8 bit condition code register CCR Figure 2 1 Programming Model 2 1 1 Accumulators General purpose 8 bit accumulators A and B are used to hold operands and results of operations Some instructions treat the combination of these two 8 bit accumulators A B as a 16 bit double accumulator D 7 15...

Page 16: ...t address of the last stack location used Normally the SP is initialized by one of the first instructions in an application program The stack grows downward from the address pointed to by the SP Each time a byte is pushed onto the stack the stack pointer is automatically decremented and each time a byte is pulled from the stack the stack pointer is automatically incremented When a subroutine is ca...

Page 17: ...on Specialized usages are described in the relevant portions of this manual and in SECTION 6 INSTRUCTION GLOSSARY 2 1 5 1 S Control Bit Setting the S bit disables the STOP instruction Execution of a STOP instruction caus es the on chip oscillator to stop This may be undesirable in some applications If the CPU encounters a STOP instruction while the S bit is set it is treated like a no oper ation N...

Page 18: ...terrupts during the interrupt service routine The I bit is set after the registers are stacked but before the interrupt vector is fetched Normally an RTI instruction at the end of the interrupt service routine restores register values that were present before the interrupt occurred Since the CCR is stacked be fore the I bit is set the RTI normally clears the I bit and thus re enables interrupts In...

Page 19: ... memory expansion scheme that increases the standard space by means of predefined windows in address space The CPU12 has special instructions that sup port use of expanded memory See SECTION 10 MEMORY EXPANSION for more in formation Eight bit values can be stored at any odd or even byte address in available memory Sixteen bit values are stored in memory as two consecutive bytes the high byte occu ...

Page 20: ...MOTOROLA OVERVIEW CPU12 2 6 REFERENCE MANUAL ...

Page 21: ...it relative offset from the current pc is supplied in the instruction Indexed 5 bit offset INST oprx5 xysp IDX 5 bit signed constant offset from x y sp or pc Indexed pre decrement INST oprx3 xys IDX Auto pre decrement x y or sp by 1 8 Indexed pre increment INST oprx3 xys IDX Auto pre increment x y or sp by 1 8 Indexed post decrement INST oprx3 xys IDX Auto post decrement x y or sp by 1 8 Indexed p...

Page 22: ...ue one 16 bit word at a time during normal program fetch cycles Since program data is read into the instruction queue several cycles be fore it is needed when an immediate addressing mode operand is called for by an in struction it is already present in the instruction queue The pound symbol is used to indicate an immediate addressing mode operand One very common programming error is to accidental...

Page 23: ...med to be zero Examples LDAA 55 This is a very basic example of direct addressing The value 55 is taken to be the low order half of an address in the range 0000 through 00FF The high order half of the address is assumed to be zero During execution of this instruction the CPU com bines the value 55 from the instruction with the assumed value of 00 to form the ad dress 0055 which is then used to acc...

Page 24: ... offset is added to the address of the next memory location after the offset to form an effective address and execution continues at that address if all the bits in memory that correspond to a one in the mask are not in the specified state execution continues with the instruction immediately fol lowing the branch instruction Both 8 bit and 16 bit offsets are signed two s complement numbers to supp...

Page 25: ...ister in all indexed operations The program counter can be used as an index register in all but autoincrement and autodecrement modes A B or D accumulators can be used for accumulator offsets Automatic pre or post increment or pre or post decrement by 8 to 8 A choice of 5 9 or 16 bit signed constant offsets Use of two new indexed indirect modes Indexed indirect mode with 16 bit offset Indexed indi...

Page 26: ...ll be 1000 and Y will still be 2000 after execution of these in structions In the first example A will be loaded with the value from address 1000 In the second example the value from the B accumulator will be stored at address 1FF8 2000 8 Table 3 2 Summary of Indexed Operations Postbyte Code xb Source Code Syntax Comments rr 00 X 01 Y 10 SP 11 PC rr0nnnnn r n r n r 5 bit constant offset n 16 to 15...

Page 27: ... requires an extra instruction byte and thus an extra execution cycle The 9 bit signed offset used in the CPU12 covers the same range of positive offsets as the M68HC11 and adds negative offset capability The CPU12 can use X Y SP or PC as the base index register 3 8 3 16 Bit Constant Offset Indexed Addressing This indexed addressing mode uses a 16 bit offset which is added to the base index regist...

Page 28: ...s the memory location affected by the instruction then change the value of the index register The CPU12 allows the index register to be incremented or decremented by any integer value in the ranges 8 through 1 or 1 through 8 The value need not be related to the size of the operand for the current instruction These instructions can be used to incor porate an index adjustment into an existing instru...

Page 29: ...register can be X Y SP or PC and the accumulator can be either of the 8 bit accumulators A or B or the 16 bit D accu mulator Example LDAA B X This instruction internally adds B to X to form the address from which A will be loaded B and X are not changed by this instruction This example is similar to the following two instruction combination in an M68HC11 ABX LDAA 0 X However this two instruction s...

Page 30: ...modes that are not allowed are those with an im mediate mode destination the operand of an immediate mode instruction is data not an address For indexed moves the reference index register may be X Y SP or PC Move instructions do not support indirect modes or 9 or 16 bit offset modes requiring extra extension bytes There are special considerations when using PC relative ad dressing with move instru...

Page 31: ...ree addressing modes The BCLR and BSET instructions use an 8 bit mask to determine which bits in a mem ory byte are to be changed The mask must be supplied with the instruction as an im mediate mode value The memory location to be modified can be specified by means of direct extended or indexed addressing modes The BRCLR and BRSET instructions use an 8 bit mask to test the states of bits in a memo...

Page 32: ...panded memory devices also have an 8 bit program page register PPAGE which allows up to 256 16 Kbyte program memory pages to be switched into and out of the program memory window This provides for up to 4 Megabytes of paged program memory The CPU12 instruction set includes CALL and RTC return from call instructions which greatly simplify the use of expanded memory space These instructions also ex ...

Page 33: ... of independent fetches yet maintains a straightforward relationship between bus and execution cycles There are two 16 bit queue stages and one 16 bit buffer Program information is fetched in aligned 16 bit words Unless buffering is required program information is first queued into stage 1 then advanced to stage 2 for execution At least two words of program information are available to the CPU whe...

Page 34: ...ces to stage 2 and stage 1 is loaded with a word of program information from the data bus The information was requested two bus cy cles earlier but has only become available this cycle due to access delay 4 2 4 Advance and Load from Buffer The content of queue stage 1 advances to stage 2 and stage 1 is loaded with a word of program information from the buffer The information in the buffer was latc...

Page 35: ...the address then perform three program word fetches to refill the queue The first two words fetched are queued during the second and third cycles of the sequence The third fetch cycle is performed in anticipation of a queue advance which may occur during the fourth cycle of the sequence If the queue is not yet ready to advance at that time the third word of program information is held in the buffe...

Page 36: ...etched are loaded into the instruction queue during the second and third cycles of the sequence The third fetch cycle is performed in antici pation of a queue advance which may occur during the first cycle of the next instruc tion If the queue is not yet ready to advance at that time the third word of program information is held in the buffer 4 3 3 2 Long Branches The not taken case for all long b...

Page 37: ... is overwritten by subsequent fetches in the not taken case 4 3 3 4 Loop Primitives The loop primitive instructions test a counter value in a register or accumulator and branch to an address specified by a 9 bit relative offset contained in the instruction if a specified pre condition is met There are auto increment and auto decrement ver sions of the instructions The test and increment decrement ...

Page 38: ...MOTOROLA INSTRUCTION QUEUE CPU12 4 6 REFERENCE MANUAL ...

Page 39: ...c and logic instructions aid stacking operations indexing BCD calcu lation and condition code register manipulation There are also dedicated instructions for multiply and accumulate operations table interpolation and specialized fuzzy logic operations that involve mathematical calculations Refer to SECTION 6 INSTRUCTION GLOSSARY for detailed information about indi vidual instructions APPENDIX A IN...

Page 40: ...umber is copied from accumulator A accumulator B or the con dition codes register to accumulator D the X index register the Y index register or the stack pointer All the bits in the upper byte of the 16 bit result are given the value of the MSB of the 8 bit number SECTION 6 INSTRUCTION GLOSSARY contains information concerning other transfers and exchanges between 8 and 16 bit registers Table 5 2 i...

Page 41: ...rs and memory Special instructions support index calculation Instruc tions that subtract the CCR carry bit facilitate multiple precision computation Refer to Table 5 4 for addition and subtraction instructions Table 5 2 Transfer and Exchange Instructions Transfer Instructions Mnemonic Function Operation TAB Transfer A to B A B TAP Transfer A to CCR A CCR TBA Transfer B to A B A TFR Transfer Regist...

Page 42: ...ning automatic counter branches Table 5 6 is a summary of decrement and incre ment instructions Table 5 4 Addition and Subtraction Instructions Addition Instructions Mnemonic Function Operation ABA Add A to B A B A ABX Add B to X B X X ABY Add B to Y B Y Y ADCA Add with Carry to A A M C A ADCB Add with Carry to B B M C B ADDA Add without Carry to A A M A ADDB Add without Carry to B B M B ADDD Add ...

Page 43: ...nction Operation DEC Decrement Memory M 01 M DECA Decrement A A 01 A DECB Decrement B B 01 B DES Decrement SP SP 0001 SP DEX Decrement X X 0001 X DEY Decrement Y Y 0001 Y Increment Instructions Mnemonic Function Operation INC Increment Memory M 01 M INCA Increment A A 01 A INCB Increment B B 01 B INS Increment SP SP 0001 SP INX Increment X X 0001 X INY Increment Y Y 0001 Y Table 5 7 Compare and Te...

Page 44: ...omplement and negate instructions Table 5 8 Boolean Logic Instructions Mnemonic Function Operation ANDA AND A with Memory A M A ANDB AND B with Memory B M B ANDCC AND CCR with Memory Clear CCR Bits CCR M CCR EORA Exclusive OR A with Memory A M A EORB Exclusive OR B with Memory B M B ORAA OR A with Memory A M A ORAB OR B with Memory B M B ORCC OR CCR with Memory Set CCR Bits CCR M CCR Table 5 9 Cle...

Page 45: ...cumulator or in memory BITA and BITB provide a convenient means of testing bits without altering the value of either operand Table 5 11 is a summary of bit test and manipulation instructions Table 5 10 Multiplication and Division Instructions Multiplication Instructions Mnemonic Function Operation EMUL 16 by 16 Multiply Unsigned D Y Y D EMULS 16 by 16 Multiply Signed D Y Y D MUL 8 by 8 Multiply Un...

Page 46: ... Logic Shift Left A Logic Shift Left B LSLD Logic Shift Left D LSR LSRA LSRB Logic Shift Right Memory Logic Shift Right A Logic Shift Right B LSRD Logic Shift Right D Arithmetic Shifts Mnemonic Function Operation ASL ASLA ASLB Arithmetic Shift Left Memory Arithmetic Shift Left A Arithmetic Shift Left B ASLD Arithmetic Shift Left D ASR ASRA ASRB Arithmetic Shift Right Memory Arithmetic Shift Right ...

Page 47: ...EV in struction treats all rules as equally important The REVW instruction allows each rule to have a separate weighting factor The two rule evaluation instructions also differ in the way rules are encoded into the knowledge base Because they require a number of cycles to execute rule evaluation instructions can be interrupted Once the interrupt has been serviced instruction execution resumes at t...

Page 48: ...tput is an 8 bit offset from a base address in Y FE separates rule inputs from rule outputs FF terminates the rule list REV can be interrupted REVW MIN MAX Rule Evaluation Find smallest rule input MIN Multiply by a rule weighting factor optional Store to rule outputs unless fuzzy output is larger MAX Each rule input is the 16 bit address of a fuzzy input Each rule output is the 16 bit address of a...

Page 49: ...e digital filters and defuzzification routines that use 16 bit operands The WAV instruction incorporates an 8 to 16 bit multiply and accumulate operation that obtains a numerator for the weighted average calculation The EMACS instruction can auto mate this portion of the averaging operation when 16 bit operands are used Table 5 15 shows the EMACS instruction Table 5 14 Minimum and Maximum Instruct...

Page 50: ...nt left of the MSB so each line seg ment is effectively divided into 256 smaller segments During instruction execution the change in y between the beginning and end of the segment a signed byte for TBL or a signed word for ETBL is multiplied by the content of the B accumulator to obtain an intermediate delta y term The result stored in the A accumulator by TBL and in the D accumulator by ETBL is t...

Page 51: ...tion of condition code register bits 5 18 1 Short Branch Instructions Short branch instructions operate as follows When a specified condition is met a signed 8 bit offset is added to the value in the program counter Program execution continues at the new address The numeric range of short branch offset values is 80 128 to 7F 127 from the address of the next memory location after the offset value T...

Page 52: ...nus N 1 BNE Branch if Not Equal Z 0 BPL Branch if Plus N 0 BVC Branch if Overflow Clear V 0 BVS Branch if Overflow Set V 1 Unsigned Branches Mnemonic Function Relation Equation or Operation BHI Branch if Higher R M C Z 0 BHS Branch if Higher or Same R M C 0 BLO Branch if Lower R M C 1 BLS Branch if Lower or Same R M C Z 1 Signed Branches Mnemonic Function Relation Equation or Operation BGE Branch ...

Page 53: ...h if Minus N 1 LBNE Long Branch if Not Equal Z 0 LBPL Long Branch if Plus N 0 LBVC Long Branch if Overflow Clear V 0 LBVS Long Branch if Overflow Set V 1 Unsigned Branches Mnemonic Function Equation or Operation LBHI Long Branch if Higher C Z 0 LBHS Long Branch if Higher or Same C 0 LBLO Long Branch if Lower Z 1 LBLS Long Branch if Lower or Same C Z 1 Signed Branches Mnemonic Function Equation or ...

Page 54: ...ion after the offset value Table 5 20 is a summary of loop primitive branches Table 5 19 Bit Condition Branch Instructions Mnemonic Function Equation or Operation BRCLR Branch if Selected Bits Clear M mm 0 BRSET Branch if Selected Bits Set M mm 0 Table 5 20 Loop Primitive Instructions Mnemonic Function Equation or Operation DBEQ Decrement counter and branch if 0 counter A B D X Y or SP counter 1 c...

Page 55: ...ks the val ue in the PPAGE register and the return address then writes a new value to PPAGE to select the memory page where the subroutine resides The page value is an imme diate operand in all addressing modes except indexed indirect modes in these modes an operand points to locations in memory where the new page value and subroutine address are stored The RTC instruction is used to terminate sub...

Page 56: ... in all 256 positions in the page 1 opcode map but only 54 of the 256 positions on page 2 of the opcode map are used If the CPU attempts to execute one of the un implemented opcodes on page 2 an opcode trap interrupt occurs Traps are essen tially interrupts that share the FFF8 FFF9 interrupt vector The RTI instruction is used to terminate all exception handlers including interrupt ser vice routine...

Page 57: ... Memory M M 1 SP LDX Load X from Memory M M 1 X LDY Load Y from Memory M M 1 Y LEAS Load Effective Address into SP Effective Address SP LEAX Load Effective Address into X Effective Address X LEAY Load Effective Address into Y Effective Address Y Store Instructions Mnemonic Function Operation STS Store SP in Memory SP M M 1 STX Store X in Memory X M M 1 STY Store Y in Memory Y M M 1 Transfer Instru...

Page 58: ... 25 is a summary of pointer and index instructions Table 5 24 Stacking Instructions Stack Pointer Instructions Mnemonic Function Operation CPS Compare SP to Memory SP M M 1 DES Decrement SP SP 1 SP INS Increment SP SP 1 SP LDS Load SP M M 1 SP LEAS Load Effective Address into SP Effective Address SP STS Store SP SP M M 1 TSX Transfer SP to X SP X TSY Transfer SP to Y SP Y TXS Transfer X to SP X SP...

Page 59: ...stem clock signals continue to run Table 5 25 Pointer and Index Calculation Instructions Mnemonic Function Operation LEAS Load Result of Indexed Addressing Mode Effective Address Calculation into Stack Pointer r Constant SP or r Accumulator SP r X Y SP or PC LEAX Load Result of Indexed Addressing Mode Effective Address Calculation into X Index Register r Constant X or r Accumulator X r X Y SP or P...

Page 60: ... Null operations are often used to replace other instructions during software debugging Replacing conditional branch instructions with BRN for instance permits testing a de cision making routine without actually taking the branches Table 5 28 shows the BGND and NOP instructions Table 5 27 Stop and Wait Instructions Mnemonic Function Operation STOP Stop SP 2 SP RTNH RTNL M SP M SP 1 SP 2 SP YH YL M...

Page 61: ...ode S X H N Set if MSB of resu Z Set if result is 00 V 0 Cleared Addressing Modes Machine Code an Load Inde Operation M M 1 Description Loads the most significa memory at the addres Condition Codes and Boolean Form LDX Obje X LDX LDX LDX LDX LDX LDX LDX LDX opr16i opr8a opr16a oprx0_xysp oprx9 xysp oprx16 xysp D xysp oprx16 xysp IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CE jj DE d FE h EE E E EX GLO PG...

Page 62: ...ation Status bit may be changed by operation but the final state is not defined Status bit used for a special purpose dd 8 bit direct address 0000 to 00FF High byte assumed to be 00 ee High order byte of a 16 bit constant offset for indexed addressing eb Exchange Transfer post byte ff Low order eight bits of a 9 bit signed constant offset for indexed addressing or low order byte of a 16 bit consta...

Page 63: ...nclude a space or comma For example the groups xysp and oprx0_xysp are both valid but the two groups oprx0 xysp are not valid be cause there is a space between them Permitted syntax is described below The definition of a legal label or expression varies from assembler to assembler As semblers also vary in the way CPU registers are specified Refer to assembler docu mentation for detailed informatio...

Page 64: ...ed MCU system Some assemblers re quire a symbol before this value rel8 Any label or expression that refers to an address that is within 256 to 255 loca tions from the next address after the last byte of object code for the current instruc tion The assembler will calculate the 8 bit signed offset and include it in the object code for this instruction rel9 Any label or expression that refers to an a...

Page 65: ...ntroller or the background debug system to perform single cycle accesses without disturbing the CPU g Read 8 bit PPAGE register These cycles are only used with the CALL instruc tion to read the current value of the PPAGE register and are not visible on the external bus Since the PPAGE register is an internal 8 bit register these cycles are never stretched I Read indirect pointer Indexed indirect i...

Page 66: ...pro grammed for slow memory r 8 bit data read These cycles are stretched only when controlled by a chip select circuit programmed for slow memory R 16 bit data read These cycles are extended to two bus cycles if the MCU is op erating with an 8 bit external data bus and the corresponding data is stored in external memory There can be additional stretching when the address space is assigned to a chi...

Page 67: ...saligned accesses to a memory that is not designed for single cycle misaligned access x 8 bit conditional write These cycles are either data write cycles or free cycles depending upon the data and flow of the REV or REVW instruction These cy cles are only stretched when controlled by a chip select circuit programmed for slow memory Special Notation for Branch Taken Not Taken Cases PPP P Short bran...

Page 68: ...dition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ABA Add Accumulator B To Accumulator A ABA S X H I N Z V C H A3 B3 B3 R3 R3 A3 Set if there was a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 B7 R7 A7 B7 R7 Set if a two s complement overflow resulted from the operation cleared othe...

Page 69: ...truction allows A B D or a constant to be added to X For compati bility with the M68HC11 the mnemonic ABX is translated into the LEAX B X instruction by the assembler Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times ABX Add Accumulator B to Index Register X ABX S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail ABX translat...

Page 70: ...truction allows A B D or a constant to be added to Y For compati bility with the M68HC11 the mnemonic ABY is translated into the LEAY B Y instruction by the assembler Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times ABY Add Accumulator B to Index Register Y ABY S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail ABY translat...

Page 71: ... I N Z V C H X3 M3 M3 R3 R3 X3 Set if there was a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if there was a carry from the MSB of the result cleared otherwise Source Form Address Mode Object Code C...

Page 72: ... I N Z V C H X3 M3 M3 R3 R3 X3 Set if there was a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if there was a carry from the MSB of the result cleared otherwise Source Form Address Mode Object Code C...

Page 73: ... R3 X3 Set if there was a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if there was a carry from the MSB of the result cleared otherwise Source Form Address Mode Object Code Cycles Access Detail ADDA...

Page 74: ... R3 X3 Set if there was a carry from bit 3 cleared otherwise N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if there was a carry from the MSB of the result cleared otherwise Source Form Address Mode Object Code Cycles Access Detail ADDB...

Page 75: ...Double Accumulator ADDD S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if two s complement overflow resulted from the operation cleared otherwise C D15 M15 M15 R15 R15 D15 Set if there was a carry from the MSB of the result cleared otherwise Source Form Address Mode Object Code Cycles Access Detail ADDD opr16i...

Page 76: ...ion Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ANDA Logical AND A ANDA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail ANDA opr8i ANDA opr8a ANDA opr16a ANDA oprx0_xysp ANDA oprx9 xysp ANDA oprx16 xysp ANDA D xysp ANDA oprx16 xysp IMM DIR...

Page 77: ...ion Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ANDB Logical AND B ANDB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail ANDB opr8i ANDB opr8a ANDB opr16a ANDB oprx0_xysp ANDB oprx9 xysp ANDB oprx16 xysp ANDB D xysp ANDB oprx16 xysp IMM DIR...

Page 78: ...e mask are not changed by the ANDCC operation If the I mask bit is cleared there is a one cycle delay before the system allows interrupt requests This prevents interrupts from occurring be tween instructions in the sequences CLI WAI and CLI SEI CLI is equiv alent to ANDCC EF Condition Codes and Boolean Formulas Condition code bits are cleared if the corresponding bit was zero before the operation ...

Page 79: ...t if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C M7 Set if the MSB of M was set before the shift cleared otherwise Source Form Address Mode Object Code Cycles Access Detail ASL opr16a ASL oprx0_xysp ASL...

Page 80: ...ine Code and Execution Times ASLA Arithmetic Shift Left A same as LSLA ASLA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C A7 Set if the MSB of A was set before the shift cleared o...

Page 81: ...ine Code and Execution Times ASLB Arithmetic Shift Left B same as LSLB ASLB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared other wise for values of N and C after the shift C B7 Set if the MSB of B was set before the shift cleared o...

Page 82: ... Execution Times ASLD Arithmetic Shift Left Double Accumulator same as LSLD ASLD S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C D15 Set if the MSB of D was set before the shift c...

Page 83: ...etic Shift Right Memory ASR S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared other wise for values of N and C after the shift C M0 Set if the LSB of M was set before the shift cleared otherwise Source Form Address Mode Object Code Cy...

Page 84: ...t Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ASRA Arithmetic Shift Right A ASRA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C A0 Set if...

Page 85: ...t Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ASRB Arithmetic Shift Right B ASRB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C B0 Set if...

Page 86: ... instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z N V 1 r m BGT 2E Signed r m BLT 2D N V 1 r m BGE 2C Signed r m BHI 22 C Z 0 r m BLS 23 Unsigned r m...

Page 87: ...ulas Addressing Modes Machine Code and Execution Times BCLR Clear Bits in Memory BCLR S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode1 Notes 1 Indirect forms of indexed addressing cannot be used with this instruction Object Code Cycles Access Detail BCLR opr8a msk8 BCLR opr16a msk8 BCLR oprx0_xysp msk8 B...

Page 88: ...nstruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z N V 1 r m BGT 2E Signed r m BLT 2D N V 1 r m BGE 2C Signed r m BHI 22 C Z 0 r m BLS 23 Unsigned r m B...

Page 89: ...on queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z N V 1 r m BGT 2E Signed r m BLT 2D N V 1 r m BGE 2C Signed r m BHI 22 C Z 0 r m BLS 23 Unsigned r m BHS BCC 2...

Page 90: ...e Object Code Cycles Access Detail BGE rel8 REL 2C rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ...

Page 91: ...ue stored in TMP2 already points to the instruction that would have executed next had BDM not become active If active BDM is triggered just as a BGND instruction is about to execute the BDM firmware does increment TMP2 but the change does not affect resumption of normal execution While BDM is active the CPU executes debugging commands received via a special single wire serial interface BDM is term...

Page 92: ...de Cycles Access Detail BGT rel8 REL 2E rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m...

Page 93: ...ource Form Address Mode Object Code Cycles Access Detail BHI rel8 REL 22 rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m...

Page 94: ...N Z V C Source Form Address Mode Object Code Cycles Access Detail BHS rel8 REL 24 rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C ...

Page 95: ...tent of the memory location is affected Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times BITA Bit Test A BITA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail BITA opr8i BITA opr8a BITA opr16a BITA oprx0_xysp BITA oprx9 xysp BITA oprx1...

Page 96: ...tent of the memory location is affected Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times BITB Bit Test B BITB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail BITB opr8i BITB opr8a BITB opr16a BITB oprx0_xysp BITB oprx9 xysp BITB oprx1...

Page 97: ...Code Cycles Access Detail BLE rel8 REL 2F rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r...

Page 98: ...C Source Form Address Mode Object Code Cycles Access Detail BLO rel8 REL 25 rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 ...

Page 99: ... Z V C Source Form Address Mode Object Code Cycles Access Detail BLS rel8 REL 23 rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N...

Page 100: ...ccess Detail BLT rel8 REL 2D rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Sig...

Page 101: ...on queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z N V 1 r m BGT 2E Signed r m BLT 2D N V 1 r m BGE 2C Signed r m BHI 22 C Z 0 r m BLS 23 Unsigned r m BHS BCC 2...

Page 102: ...truction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z N V 1 r m BGT 2E Signed r m BLT 2D N V 1 r m BGE 2C Signed r m BHI 22 C Z 0 r m BLS 23 Unsigned r m BHS...

Page 103: ...n queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z N V 1 r m BGT 2E Signed r m BLT 2D N V 1 r m BGE 2C Signed r m BHI 22 C Z 0 r m BLS 23 Unsigned r m BHS BCC 24...

Page 104: ...aken than when it is not because the instruction queue must be refilled before execution resumes at the new address Since the BRA branch condition is always satisfied the branch is always taken and the instruction queue must al ways be refilled See 3 7 Relative Addressing Mode for details of branch execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execu...

Page 105: ...offset rr which is the last byte of the in struction object code See 3 7 Relative Addressing Mode for details of branch execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times BRCLR Branch if Bits Cleared BRCLR S X H I N Z V C Source Form Address Mode1 Notes 1 Indirect forms of indexed addressing cannot be used with this instruction Object Cod...

Page 106: ...n compiler imple mentations Execution time is longer when a conditional branch is taken than when it is not because the instruction queue must be refilled before execution resumes at the new address Since the BRN branch condition is never satisfied the branch is never taken and only a single program fetch is needed to update the instruction queue See 3 7 Relative Addressing Mode for details of bra...

Page 107: ...relative offset rr which is the last byte of the instruction object code See 3 7 Relative Addressing Mode for details of branch execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times BRSET Branch if Bits Set BRSET S X H I N Z V C Source Form Address Mode1 Notes 1 Indirect forms of indexed addressing cannot be used with this instruction Object...

Page 108: ...Modes Machine Code and Execution Times BSET Set Bit s in Memory BSET S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode1 Notes 1 Indirect forms of indexed addressing cannot be used with this instruction Object Code Cycles Access Detail BSET opr8a msk8 BSET opr16a msk8 BSET oprx0_xysp msk8 BSET oprx9 xysp ms...

Page 109: ...wo bytes of the return ad dress to be stacked Stacks the return address the SP points to the high order byte of the return address Branches to a location determined by the branch offset Subroutines are normally terminated with an RTS instruction which re stores the return address from the stack Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times BSR...

Page 110: ...l BVC rel8 REL 28 rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE...

Page 111: ... rel8 REL 29 rr 3 1 PPP P1 Notes 1 PPP P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m BGT 2E Z N V 0 r m BLE 2F Signed r m BGE 2C N V 0 r m BLT 2D Signed r m BEQ 27 Z 1 r m BNE 26 Signed r m BLE 2F Z...

Page 112: ...to be stacked Stacks the content of PPAGE Writes a new page value supplied by the instruction to PPAGE Transfers control to the subroutine In indexed indirect modes the subroutine address and the PPAGE value are fetched from memory in the order M high byte M low byte and new PPAGE value Expanded memory subroutines must be terminated by an RTC instruc tion which restores the return address and PPAG...

Page 113: ...changed Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times CBA Compare Accumulators CBA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 B7 R7 A7 B7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C A7 B7 B7 R7 R7 A7 Set if there was a borrow from the MSB of the resul...

Page 114: ...o clear any combination of bits in the CCR in one operation CLC can be used to set up the C bit prior to a shift or rotate instruction involving the C bit Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times CLC Clear Carry CLC S X H I N Z V C 0 C 0 Cleared Source Form Address Mode Object Code Cycles Access Detail CLC translates to ANDCC FE IMM 10 FE 1 P ...

Page 115: ... is a one cycle bus clock delay in the clearing mechanism for the I bit so that if inter rupts were previously disabled the next instruction after a CLI will always be executed even if there was an interrupt pending prior to exe cution of the CLI instruction Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times CLI Clear Interrupt Mask CLI S X H I N Z V C 0 I 0 Cle...

Page 116: ...s Machine Code and Execution Times CLR Clear Memory CLR S X H I N Z V C 0 1 0 0 N 0 Cleared Z 1 Set V 0 Cleared C 0 Cleared Source Form Address Mode Object Code Cycles Access Detail CLR opr16a CLR oprx0_xysp CLR oprx9 xysp CLR oprx16 xysp CLR D xysp CLR oprx16 xysp EXT IDX IDX1 IDX2 D IDX IDX2 79 hh ll 69 xb 69 xb ff 69 xb ee ff 69 xb 69 xb ee ff 3 2 3 3 5 5 wOP Pw PwO PwP PIfPw PIPPw ...

Page 117: ... bits in accumulator A are cleared to zero Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times CLRA Clear A CLRA S X H I N Z V C 0 1 0 0 N 0 Cleared Z 1 Set V 0 Cleared C 0 Cleared Source Form Address Mode Object Code Cycles Access Detail CLRA INH 87 1 O ...

Page 118: ... bits in accumulator B are cleared to zero Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times CLRB Clear B CLRB S X H I N Z V C 0 1 0 0 N 0 Cleared Z 1 Set V 0 Cleared C 0 Cleared Source Form Address Mode Object Code Cycles Access Detail CLRB INH C7 1 O ...

Page 119: ... The ANDCC instruction can be used to clear any combination of bits in the CCR in one operation Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times CLV Clear Two s Complement Overflow Bit CLV S X H I N Z V C 0 V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail CLV translates to ANDCC FD IMM 10 FD 1 P ...

Page 120: ... X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if there was a borrow from the MSB of the result cleared otherwise Source Form Address Mode Object Code Cycles Access Detail CMPA opr8i CMPA opr8a CMPA opr16a CMPA oprx0_xy...

Page 121: ... X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if there was a borrow from the MSB of the result cleared otherwise Source Form Address Mode Object Code Cycles Access Detail CMPB opr8i CMPB opr8a CMPB opr16a CMPB oprx0_xy...

Page 122: ...l signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times COM Complement Memory COM S X H I N Z V C 0 1 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared C 1 Set for M6800 compatibility Source Form Address Mode Object Code Cycles Access Detail COM opr16a COM oprx0_xysp COM oprx9 xysp COM ...

Page 123: ...BNE branches can be expected to perform consistently After operation on two s complement values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times COMA Complement A COMA S X H I N Z V C 0 1 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared C 1 Set for M6800 compatibility Source F...

Page 124: ...BNE branches can be expected to perform consistently After operation on two s complement values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times COMB Complement B COMB S X H I N Z V C 0 1 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared C 1 Set for M6800 compatibility Source F...

Page 125: ...V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if two s complement overflow resulted from the operation cleared otherwise C D15 M15 M15 R15 R15 D15 Set if the absolute value of the content of memory is larger than the absolute value of the accumulator cleared otherwise Source Form Address Mode Object Code Cycles Access De...

Page 126: ... Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V S15 M15 R15 S15 M15 R15 Set if two s complement overflow resulted from the operation cleared otherwise C S15 M15 M15 R15 R15 S15 Set if the absolute value of the content of memory is larger than the absolute value of the SP cleared otherwise Source Form Address Mode Object Code Cycles Access Detail C...

Page 127: ...X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V X15 M15 R15 X15 M15 R15 Set if two s complement overflow resulted from the operation cleared otherwise C X15 M15 M15 R15 R15 X15 Set if the absolute value of the content of memory is larger than the absolute value of the index register cleared otherwise Source Form Address Mode Object Code Cyc...

Page 128: ...Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V Y15 M15 R15 Y15 M15 R15 Set if two s complement overflow resulted from the operation cleared otherwise C Y15 M15 M15 R15 R15 Y15 Set if the absolute value of the content of memory is larger than the absolute value of the index register cleared otherwise Source Form Address Mode Object Code Cycles Access Detai...

Page 129: ... on BCD operands The correction factor in column 5 is added to the accumulator to restore the result of an operation on two BCD operands to a valid BCD value and to set or clear the C bit All val ues are in hexadecimal Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times DAA Decimal Adjust A DAA 1 2 3 4 5 6 Initial C Bit Value Value of A 7 4 Initial H Bit Value Va...

Page 130: ...ration is to be performed Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times DBEQ Decrement and Branch if Equal to Zero DBEQ S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Encoding for lb is summarized in the following table Bit 3 is not used don t care bit 5 selects branch on zero DBEQ 0 or not zero DBNE 1 versions and bit 4 is the ...

Page 131: ...ich operation is to be performed Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times DBNE Decrement and Branch if Not Equal to Zero DBNE S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Encoding for lb is summarized in the following table Bit 3 is not used don t care bit 5 selects branch on zero DBEQ 0 or not zero DBNE 1 versions and bi...

Page 132: ...essing Modes Machine Code and Execution Times DEC Decrement Memory DEC S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if there was a two s complement overflow as a result of the operation cleared otherwise Two s complement overflow occurs if and only if M was 80 before the operation Source Form Address Mode Object Code Cycles Access De...

Page 133: ...ed as a loop counter in multiple pre cision computations Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times DECA Decrement A DECA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if there was a two s complement overflow as a result of the operation cleared otherwise Two s complement overflow occurs if ...

Page 134: ...ed as a loop counter in multiple pre cision computations Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times DECB Decrement B DECB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if there was a two s complement overflow as a result of the operation cleared otherwise Two s complement overflow occurs if ...

Page 135: ... as DEX or DEY in structions do Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times DES Decrement Stack Pointer DES S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail DES translates to LEAS 1 SP IDX 1B 9F 2 PP1 Notes 1 Due to internal CPU requirements the program word fetch is performed twice to the same address during this in...

Page 136: ...the LEAX instruction is more flexible DEX requires only one byte of object code Only the Z bit is set or cleared according to the result of this operation Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times DEX Decrement Index Register X DEX S X H I N Z V C Z Set if result is 0000 cleared otherwise Source Form Address Mode Object Code Cycles Access Detail DEX INH...

Page 137: ...the LEAY instruction is more flexible DEY requires only one byte of object code Only the Z bit is set or cleared according to the result of this operation Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times DEY Decrement Index Register Y DEY S X H I N Z V C Z Set if result is 0000 cleared otherwise Source Form Address Mode Object Code Cycles Access Detail DEY INH...

Page 138: ...e states of the N and Z bits in the CCR are undefined Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EDIV Extended Divide 32 Bit by 16 Bit Unsigned EDIV S X H I N Z V C N Set if MSB of result is set cleared otherwise Undefined after over flow or division by zero Z Set if result is 0000 cleared otherwise Undefined after overflow or division by zero V Set if t...

Page 139: ...tes of the N and Z bits in the CCR are undefined Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EDIVS Extended Divide 32 Bit by 16 Bit Signed EDIVS S X H I N Z V C N Set if MSB of result is set cleared otherwise Undefined after overflow or division by zero Z Set if result is 0000 cleared otherwise Undefined after overflow or division by zero V Set if the res...

Page 140: ...bytes of the source operands The most significant byte of the 32 bit result is specified by an extended address supplied with the instruction Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMACS Extended Multiply and Accumulate Signed 16 Bit by 16 Bit to 32 Bit EMACS S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00000000 ...

Page 141: ...t decrement variations of indexed addressing facilitate finding the largest value in a list of values Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMAXD Place Larger of Two Unsigned 16 Bit Values in Accumulator D EMAXD S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if ...

Page 142: ... flexibility in specifying the address of the operand Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMAXM Place Larger of Two Unsigned 16 Bit Values in Memory EMAXM S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if a two s complement overflow resulted from the operation...

Page 143: ...t decrement variations of indexed addressing facilitate finding the largest value in a list of values Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMIND Place Smaller of Two Unsigned 16 Bit Values in Accumulator D EMIND S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if...

Page 144: ... flexibility in specifying the address of the operand Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMINM Place Smaller of Two Unsigned 16 Bit Values in Memory EMINM S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if a two s complement overflow resulted from the operatio...

Page 145: ...n D is multiplied by the value in Y The upper 16 bits of the 32 bit result are stored in Y and the low order 16 bits of the result are stored in D The C status bit can be used to round the high order 16 bits of the result Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMUL Extended Multiply 16 Bit by 16 Bit Unsigned EMUL S X H I N Z V C N Set if the MSB of t...

Page 146: ...ied by the value Y The 16 high order bits of the 32 bit result are stored in Y and the 16 low order bits of the result are stored in D The C status bit can be used to round the high order 16 bits of the result Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EMULS Extended Multiply 16 Bit by 16 Bit Signed EMULS S X H I N Z V C N Set if the MSB of the result is...

Page 147: ...ion Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EORA Exclusive OR A EORA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail EORA opr8i EORA opr8a EORA opr16a EORA oprx0_xysp EORA oprx9 xysp EORA oprx16 xysp EORA D xysp EORA oprx16 xysp IMM DI...

Page 148: ...ion Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times EORB Exclusive OR B EORB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail EORB opr8i EORB opr8a EORB opr16a EORB oprx0_xysp EORB oprx9 xysp EORB oprx16 xysp EORB D xysp EORB oprx16 xysp IMM DI...

Page 149: ...tor B with a binary fraction radix point to left of MSB representing the ratio XL X1 X2 X1 The 16 bit unrounded result is calculated using the following expression D Y1 B Y2 Y1 Where B XL X1 X2 X1 Y1 16 bit data entry pointed to by effective address Y2 16 bit data entry pointed to by effective address 2 The intermediate value B Y2 Y1 produces a 24 bit result with the radix point between bits 7 and...

Page 150: ... by recognition of an XIRQ interrupt Addressing Modes Machine Code and Execution Times EXG Exchange Register Contents EXG S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Legal coding for eb is summarized in the following table Columns represent the high order source digit Rows represent the low order destination digit bit 3 is a don t care Values are in hexadecimal Cycles Access Deta...

Page 151: ... perform ing 32 x 16 bit integer division The result is interpreted as a binary weighted fraction which resulted from the division of a 16 bit integer by a larger 16 bit integer A result of 0001 corresponds to 0 000015 and FFFF corresponds to 0 9998 The remainder of an IDIV instruction can be resolved into a binary weighted fraction by an FDIV instruction The remainder of an FDIV instruction can b...

Page 152: ...to be performed Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times IBEQ Increment and Branch if Equal to Zero IBEQ S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Encoding for lb is summarized in the following table Bit 3 is not used don t care bit 5 selects branch on zero IBEQ 0 or not zero IBNE 1 versions and bit 0 is the sign bit o...

Page 153: ...tion is to be performed Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times IBNE Increment and Branch if Not Equal to Zero IBNE S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Encoding for lb is summarized in the following table Bit 3 is not used don t care bit 5 selects branch on zero IBEQ 0 or not zero IBNE 1 versions and bit 0 is th...

Page 154: ...ve radix points in the same positions the radix point of the quotient is to the right of bit zero In the case of di vision by zero the quotient is set to FFFF and the remainder is indeter minate Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times IDIV Integer Divide IDIV S X H I N Z V C 0 Z Set if quotient is 0000 cleared otherwise V 0 Cleared C X15 X14 X13 X12 X...

Page 155: ... only overflow case is But the highest positive value that can be represented in a 16 bit two s complement number is 32 767 7FFFF Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times IDIVS Integer Divide Signed IDIVS S X H I N Z V C N Set if MSB of result is set cleared otherwise Undefined after over flow or division by zero Z Set if quotient is 0000 cleared other...

Page 156: ...plement values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times INC Increment Memory INC S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if there is a two s complement overflow as a result of the opera tion cleared otherwise Two s complement overflow occurs if and o...

Page 157: ...BEQ BNE LBEQ and LBNE branches can be expected to perform consistently When operating on two s complement values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times INCA Increment A INCA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if there is a two s complement ove...

Page 158: ...BEQ BNE LBEQ and LBNE branches can be expected to perform consistently When operating on two s complement values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times INCB Increment B INCB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V Set if there is a two s complement ove...

Page 159: ...an INX or INY in struction would Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times INS Increment Stack Pointer INS S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail INS translates to LEAS 1 SP IDX 1B 81 2 PP1 Notes 1 Due to internal CPU requirements the program word fetch is performed twice to the same address during this i...

Page 160: ...us bit Although the LEAX instruction is more flexible INX requires only one byte of object code INX operation affects only the Z status bit Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times INX Increment Index Register X INX S X H I N Z V C Z Set if result is 0000 cleared otherwise Source Form Address Mode Object Code Cycles Access Detail INX INH 08 1 O ...

Page 161: ...us bit Although the LEAY instruction is more flexible INY requires only one byte of object code INY operation affects only the Z status bit Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times INY Increment Index Register Y INY S X H I N Z V C Z Set if result is 0000 cleared otherwise Source Form Address Mode Object Code Cycles Access Detail INY INH 02 1 O ...

Page 162: ...ended or indexed ad dressing Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times JMP Jump JMP S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail JMP opr16a JMP oprx0_xysp JMP oprx9 xysp JMP oprx16 xysp JMP D xysp JMP oprx16 xysp EXT IDX IDX1 IDX2 D IDX IDX2 06 hh ll 05 xb 05 xb ff 05 xb ee ff 05 xb 05 xb ee ff 3 3 3 4 6 6 PPP ...

Page 163: ...ctive address according to the rules for extended direct or indexed addressing Jumps to the location determined by the effective address Subroutines are normally terminated with an RTS instruction which re stores the return address from the stack Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times JSR Jump to Subroutine JSR S X H I N Z V C Source Fo...

Page 164: ...three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed r m LBLT 18 2D N V 1 r m LBGE 18 2C Signed r m LBHI 18 22 C Z 0 r m LBLS 18 23 Unsigned r m LBHS LBC...

Page 165: ...ree cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed r m LBLT 18 2D N V 1 r m LBGE 18 2C Signed r m LBHI 18 22 C Z 0 r m LBLS 18 23 Unsigned r m LBHS LBCC ...

Page 166: ...if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed r m LBLT 18 2D N V 1 r m LBGE 18 2C Signed r m LBHI 18 22 C Z 0 r m LBLS 18 23 Unsigned r m LBHS LBCC 18 24 C 0 r...

Page 167: ...PP OPO1 Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z...

Page 168: ...Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r...

Page 169: ...ccess Detail LBHI rel16 REL 18 22 qq rr 4 3 OPPP OPO1 Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18...

Page 170: ...t Code Cycles Access Detail LBHS rel16 REL 18 24 qq rr 4 3 OPPP OPO1 Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Sig...

Page 171: ...PPP OPO1 Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F ...

Page 172: ...es Access Detail LBLO rel16 REL 18 25 qq rr 4 3 OPPP OPO1 Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBE...

Page 173: ...Cycles Access Detail LBLS rel16 REL 18 23 qq rr 4 3 OPPP OPO1 Notes 1 OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m...

Page 174: ... OPPP OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT...

Page 175: ...es if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed r m LBLT 18 2D N V 1 r m LBGE 18 2C Signed r m LBHI 18 22 C Z 0 r m LBLS 18 23 Unsigned r m LBHS LBCC 18 24 C ...

Page 176: ...e cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed r m LBLT 18 2D N V 1 r m LBGE 18 2C Signed r m LBHI 18 22 C Z 0 r m LBLS 18 23 Unsigned r m LBHS LBCC 18...

Page 177: ...s if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed r m LBLT 18 2D N V 1 r m LBGE 18 2C Signed r m LBHI 18 22 C Z 0 r m LBLS 18 23 Unsigned r m LBHS LBCC 18 24 C 0...

Page 178: ...an when it is not because the instruction queue must be refilled before execution resumes at the new address Since the LBRA branch condition is always satisfied the branch is always taken and the instruction queue must al ways be refilled so execution time is always the larger value See 3 7 Relative Addressing Mode for details of branch execution Condition Codes and Boolean Formulas None affected ...

Page 179: ...BRA is also useful in com piler implementations Execution time is longer when a conditional branch is taken than when it is not because the instruction queue must be refilled before execution resumes at the new address Since the LBRN branch condition is never satisfied the branch is never taken and the queue does not need to be refilled so execution time is always the smaller value Condition Codes...

Page 180: ...O indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E S...

Page 181: ...icates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r m LBGT 18 2E Z N V 0 r m LBLE 18 2F Signed r m LBGE 18 2C N V 0 r m LBLT 18 2D Signed r m LBEQ 18 27 Z 1 r m LBNE 18 26 Signed r m LBLE 18 2F Z N V 1 r m LBGT 18 2E Signed...

Page 182: ...imes LDAA Load Accumulator A LDAA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail LDAA opr8i LDAA opr8a LDAA opr16a LDAA oprx0_xysp LDAA oprx9 xysp LDAA oprx16 xysp LDAA D xysp LDAA oprx16 xysp IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 86 ii 96 dd B6 hh ll A6 xb A6 xb ff A6 xb...

Page 183: ...imes LDAB Load Accumulator B LDAB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail LDAB opr8i LDAB opr8a LDAB opr16a LDAB oprx0_xysp LDAB oprx9 xysp LDAB oprx16 xysp LDAB D xysp LDAB oprx16 xysp IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 C6 ii D6 dd F6 hh ll E6 xb E6 xb ff E6 xb...

Page 184: ...and Boolean Formulas Addressing Modes Machine Code and Execution Times LDD Load Double Accumulator LDD S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail LDD opr16i LDD opr8a LDD opr16a LDD oprx0_xysp LDD oprx9 xysp LDD oprx16 xysp LDD D xysp LDD oprx16 xysp IMM DIR EXT ID...

Page 185: ...sing Modes Machine Code and Execution Times LDS Load Stack Pointer LDS S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail LDS opr16i LDS opr8a LDS opr16a LDS oprx0_xysp LDS oprx9 xysp LDS oprx16 xysp LDS D xysp LDS oprx16 xysp IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CF jj kk ...

Page 186: ...ssing Modes Machine Code and Execution Times LDX Load Index Register X LDX S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail LDX opr16i LDX opr8a LDX opr16a LDX oprx0_xysp LDX oprx9 xysp LDX oprx16 xysp LDX D xysp LDX oprx16 xysp IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CE jj...

Page 187: ...ssing Modes Machine Code and Execution Times LDY Load Index Register Y LDY S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail LDY opr16i LDY opr8a LDY opr16a LDY oprx0_xysp LDY oprx9 xysp LDY oprx16 xysp LDY D xysp LDY oprx16 xysp IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CD jj...

Page 188: ...ations and the SP is the referenced index register The index register is loaded with what would have gone out to the address bus in the case of a load index instruction In the case of a pre increment or pre decrement the modification is made before the index register is loaded In the case of a post increment or post decre ment modification would have taken effect after the address went out on the ...

Page 189: ... register is loaded with what would have gone out to the address bus in the case of a load indexed instruc tion In the case of a pre increment or pre decrement the modification is made before the index register is loaded In the case of a post increment or post decrement modification would have taken effect after the ad dress went out on the address bus so post modification does not affect the cont...

Page 190: ... register is loaded with what would have gone out to the address bus in the case of a load indexed instruc tion In the case of a pre increment or pre decrement the modification is made before the index register is loaded In the case of a post increment or post decrement modification would have taken effect after the ad dress went out on the address bus so post modification does not affect the cont...

Page 191: ...f MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C M7 Set if the LSB of M was set before the shift cleared otherwise Source Form Address Mode Object Code Cycles Access Detail LSL opr16a LSL oprx0_xysp LSL op...

Page 192: ... Code and Execution Times LSLA Logical Shift Left A Same as ASLA LSLA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C A7 Set if the LSB of A was set before the shift cleared otherwi...

Page 193: ... Code and Execution Times LSLB Logical Shift Left B Same as ASLB LSLB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C B7 Set if the LSB of B was set before the shift cleared otherwi...

Page 194: ...e Code and Execution Times LSLD Logical Shift Left Double Same as ASLD LSLD S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C D15 Set if the MSB of D was set before the shift cleare...

Page 195: ... C 0 N 0 Cleared Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C M0 Set if the LSB of M was set before the shift cleared otherwise Source Form Address Mode Object Code Cycles Access Detail LSR opr16a LSR oprx0_xysp LSR oprx9 xysp LSR oprx16 xysp...

Page 196: ...Addressing Modes Machine Code and Execution Times LSRA Logical Shift Right A LSRA S X H I N Z V C 0 N 0 Cleared Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C A0 Set if the LSB of A was set before the shift cleared otherwise Source Form Address...

Page 197: ...Addressing Modes Machine Code and Execution Times LSRB Logical Shift Right B LSRB S X H I N Z V C 0 N 0 Cleared Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C B0 Set if the LSB of B was set before the shift cleared otherwise Source Form Address...

Page 198: ...Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times LSRD Logical Shift Right Double LSRD S X H I N Z V C 0 N 0 Cleared Z Set if result is 0000 cleared otherwise V D0 Set if after the shift operation C is set cleared otherwise C D0 Set if the LSB of D was set before the shift cleared otherwise Source Form Address Mode Object Code Cycles Access Detail LSRD INH 49 1...

Page 199: ...ncrement decrement variations of indexed addressing facilitate finding the largest value in a list of values Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times MAXA Place Larger of Two Unsigned 8 Bit Values in Accumulator A MAXA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a tw...

Page 200: ...reat deal of flexibility in specifying the address of the operand Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times MAXM Place Larger of Two Unsigned 8 Bit Values in Memory MAXM S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operatio...

Page 201: ...int of the trapezoid and Slope_2 is the slope of the trailing side of the trapezoid The trailing side slopes up and left from Point_2 A Slope_1 or Slope_2 value of 00 indicates a special case where the membership function either starts with a grade of FF at input Point_1 or ends with a grade of FF at input Point_2 infinite slope When MEM is executed X points at Point_1 and Slope_2 is at X 3 After ...

Page 202: ...perand Auto increment decrement variations of indexed addressing facilitate finding the largest value in a list of values Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times MINA Place Smaller of Two Unsigned 8 Bit Values in Accumulator A MINA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 ...

Page 203: ...eat deal of flexibility in specifying the address of the operand Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times MINM Place Smaller of Two Unsigned 8 Bit Values in Memory MINM S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operatio...

Page 204: ... are not al lowed Indexed indirect modes for example D r are also not allowed There are special considerations when using PC relative addressing with move instructions These are discussed in 3 9 Instructions Using Multiple Modes Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times MOVB Move a Byte of Data from One Memory Location to Another MOVB S X ...

Page 205: ...and are not al lowed Indexed indirect modes for example D r are also not allowed There are special considerations when using PC relative addressing with move instructions These are discussed in 3 9 Instructions Using Multiple Modes Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times MOVW Move a Word of Data from One Memory Location to Another MOVW S...

Page 206: ...nsigned result in double accumulator D The carry flag allows rounding the most significant byte of the result through the sequence MUL ADCA 0 Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times MUL Multiply 8 Bit by 8 Bit Unsigned MUL S X H I N Z V C C R7 Set if bit 7 of the result B bit 7 is set cleared otherwise Source Form Address Mode Object Code Cycles Acces...

Page 207: ...erwise V R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a two s complement overflow from the implied subtraction from zero cleared otherwise Two s complement overflow occurs if and only if M 80 C R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a borrow in the implied subtraction from zero cleared oth erwise Set in all cases except when M 00 Source Form Address Mode Object Code Cycles Access Detail NEG opr16a NEG...

Page 208: ...X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a two s complement overflow from the implied subtraction from zero cleared otherwise Two s complement overflow occurs if and only if A 80 C R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a borrow in the implied subtraction from zero cleared oth erwise Set in all ...

Page 209: ...X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a two s complement overflow from the implied subtraction from zero cleared otherwise Two s complement overflow occurs if and only if B 80 C R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a borrow in the implied subtraction from zero cleared oth erwise Set in all ...

Page 210: ...lay although some software disciplines discourage CPU fre quency based time delays During debug NOP instructions are some times used to temporarily replace other machine code instructions thus disabling the replaced instruction s Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times NOP Null Operation NOP S X H I N Z V C Source Form Address Mode Objec...

Page 211: ...ondition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ORAA Inclusive OR A ORAA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail ORAA opr8i ORAA opr8a ORAA opr16a ORAA oprx0_xysp ORAA oprx9 xysp ORAA oprx16 xysp ORAA D xysp ORAA oprx16 xysp I...

Page 212: ...ndition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ORAB Inclusive OR B ORAB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail ORAB opr8i ORAB opr8a ORAB opr16a ORAB oprx0_xysp ORAB oprx9 xysp ORAB oprx16 xysp ORAB D xysp ORAB oprx16 xysp IM...

Page 213: ...e bits set the corresponding bit of the mask equal to one Bits correspond ing to zeros in the mask are not changed by the ORCC operation Condition Codes and Boolean Formulas Condition code bits are set if the corresponding bit was one before the operation or if the corresponding bit in the instruction provided mask is one The X interrupt mask cannot be set by any software instruction Addressing Mo...

Page 214: ...tructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull in structions can be used to restore the saved CPU registers just before re turning from the subroutine Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PSHA Push A onto Stack PSHA S X H I N Z V C Source Form Address Mode ...

Page 215: ...tructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull in structions can be used to restore the saved CPU registers just before re turning from the subroutine Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PSHB Push B onto Stack PSHB S X H I N Z V C Source Form Address Mode ...

Page 216: ...oints Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull in structions can be used to restore the saved CPU registers just before re turning from the subroutine Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PSHC Push CCR onto Stack PSHC S X H I N Z V C Source Fo...

Page 217: ...d B are stacked when an interrupt is recognized The interrupt stacking order is backward compatible with the M6800 which had no 16 bit accumulator Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull in structions can be used to restore the saved CPU registers just before re turning from the subroutine Condition Codes...

Page 218: ...d value of the high order half of X Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull in structions can be used to restore the saved CPU registers just before re turning from the subroutine Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PSHX Push Index Register ...

Page 219: ...d value of the high order half of Y Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine Complementary pull in structions can be used to restore the saved CPU registers just before re turning from the subroutine Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PSHY Push Index Register ...

Page 220: ...ed by one Pull instructions are commonly used at the end of a subroutine to re store the contents of CPU registers that were pushed onto the stack be fore subroutine execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PULA Pull A from Stack PULA S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail PULA INH 32 3 ufO ...

Page 221: ...ed by one Pull instructions are commonly used at the end of a subroutine to re store the contents of CPU registers that were pushed onto the stack be fore subroutine execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PULB Pull B from Stack PULB S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail PULB INH 33 3 ufO ...

Page 222: ...ed onto the stack be fore subroutine execution Condition Codes and Boolean Formulas Condition codes take on the value pulled from the stack except that the X mask bit cannot change from zero to one Software can leave the X bit set leave it cleared or change it from one to zero but it can only be set by a reset or by recognition of an XIRQ interrupt Addressing Modes Machine Code and Execution Times...

Page 223: ...TI instruction is execut ed The interrupt stacking order for A and B is backward compatible with the M6800 which had no 16 bit accumulator Pull instructions are commonly used at the end of a subroutine to re store the contents of CPU registers that were pushed onto the stack be fore subroutine execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution ...

Page 224: ...ed by two Pull instructions are commonly used at the end of a subroutine to re store the contents of CPU registers that were pushed onto the stack be fore subroutine execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PULX Pull Index Register X from Stack PULX S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail PULX I...

Page 225: ...ed by two Pull instructions are commonly used at the end of a subroutine to re store the contents of CPU registers that were pushed onto the stack be fore subroutine execution Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times PULY Pull Index Register Y from Stack PULY S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail PULY I...

Page 226: ... The smallest input value is the truth value of the rule Then beginning with the ad dress pointed to by the first rule consequent the truth value is compared to each successive fuzzy output value until another FE separator is en countered if the truth value is greater than the current output value it is written to the output Operation is similar to that of a MAXM instruction Rules are processed un...

Page 227: ...FE separators are encountered At the end of execution V should equal one because the last element before the FF end marker should be a rule consequent If V is equal to zero at the end of execution the rule list is incorrect Fuzzy outputs must be cleared to 00 before processing begins in order for the MAX algorithm used during consequent processing to work cor rectly Residual output values would ca...

Page 228: ...omputation is performed and the truth value is modified Then beginning with the address pointed to by the first rule consequent the truth value is compared to each successive fuzzy output value until another FFFE separator is encountered if the truth value is greater than the current output value it is written to the output Operation is similar to that of a MAXM instruction Rules are processed unt...

Page 229: ... as FFFE separators are encoun tered At the end of execution V should equal one because the last el ement before the FF end marker should be a rule consequent If V is equal to zero at the end of execution the rule list is incorrect Fuzzy outputs must be cleared to 00 before processing begins in order for the MAX algorithm used during consequent processing to work cor rectly Residual output values ...

Page 230: ...ue respectively Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ROL Rotate Left Memory ROL S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C M7 ...

Page 231: ...be used where LOW MID and HIGH refer to the low order middle and high order bytes of the 24 bit value respectively Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ROLA Rotate Left A ROLA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cle...

Page 232: ...be used where LOW MID and HIGH refer to the low order middle and high order bytes of the 24 bit value respectively Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ROLB Rotate Left B ROLB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cle...

Page 233: ...lue respectively Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times ROR Rotate Right Memory ROR S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is cleared or N is cleared and C is set cleared oth erwise for values of N and C after the shift C M...

Page 234: ... be used where LOW MID and HIGH refer to the low order middle and high order bytes of the 24 bit value respectively Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times RORA Rotate Right A RORA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is c...

Page 235: ... be used where LOW MID and HIGH refer to the low order middle and high order bytes of the 24 bit value respectively Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times RORB Rotate Right B RORB S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V N C N C N C for N and C after the shift Set if N is set and C is c...

Page 236: ...am overlay page PPAGE register and the return ad dress are restored from the stack program execution continues at the restored address For code compatibility purposes CALL and RTC also execute correctly in M68HC12 devices that do not have expanded mem ory capability Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times RTC Return from Call RTC S X H I...

Page 237: ...ending when RTI has finished restoring registers from the stack the SP is adjusted to preserve stack content and the new vector is fetched This operation is functionally identical to the same op eration in the M68HC11 where registers actually are re stacked but is faster Condition Codes and Boolean Formulas Condition codes take on the value pulled from the stack except that the X mask bit can not ...

Page 238: ...nter with a 16 bit value pulled from the stack and increments the stack pointer by two Program execution continues at the address restored from the stack Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times RTS Return from Subroutine RTS S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail RTS INH 3D 5 UfPPP ...

Page 239: ... Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times SBA Subtract Accumulators SBA S X H I N Z V C N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V A7 B7 R7 A7 B7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C A7 B7 B7 R7 R7 A7 Set if the absolute value of B is larger than the absolute value of...

Page 240: ...t is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if the absolute value of the content of memory plus previous carry is larger than the absolute value of the accumulator cleared otherwise Source Form Address Mode Object Code Cycles Access Detail SBCA opr8i S...

Page 241: ...t is set cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if the absolute value of the content of memory plus previous carry is larger than the absolute value of the accumulator cleared other wise Source Form Address Mode Object Code Cycles Access Detail SBCB opr8i ...

Page 242: ...d to set any combination of bits in the CCR in one operation SEC can be used to set up the C bit prior to a shift or rotate instruction involving the C bit Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times SEC Set Carry SEC S X H I N Z V C 1 C 1 Set Source Form Address Mode Object Code Cycles Access Detail SEC translates to ORCC 01 IMM 14 01 1 P ...

Page 243: ...of bits in the CCR in one operation When the I bit is set all maskable interrupts are inhib ited and the CPU will recognize only non maskable interrupt sources or an SWI Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times SEI Set Interrupt Mask SEI S X H I N Z V C 1 I 1 Set Source Form Address Mode Object Code Cycles Access Detail SEI translates to ORCC 10 IMM 14...

Page 244: ...C 02 The ORCC instruction can be used to set any combination of bits in the CCR in one operation Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times SEV Set Two s Complement Overflow Bit SEV S X H I N Z V C 1 V 1 Set Source Form Address Mode Object Code Cycles Access Detail SEV translates to ORCC 02 IMM 14 02 1 P ...

Page 245: ...d Boolean Formulas None affected Addressing Modes Machine Code and Execution Times SEX Sign Extend into 16 bit Register SEX S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Legal coding for eb is summarized in the following table Columns represent the high order digit and rows rep resent the low order digit in hexadecimal MSB is a don t care Cycles Access Detail SEX abc dxys INH B7 eb...

Page 246: ...on Times STAA Store Accumulator A STAA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail STAA opr8a STAA opr16a STAA oprx0_xysp STAA oprx9 xysp STAA oprx16 xysp STAA D xysp STAA oprx16 xysp DIR EXT IDX IDX1 IDX2 D IDX IDX2 5A dd 7A hh ll 6A xb 6A xb ff 6A xb ee ff 6A xb 6A ...

Page 247: ...on Times STAB Store Accumulator B STAB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail STAB opr8a STAB opr16a STAB oprx0_xysp STAB oprx9 xysp STAB oprx16 xysp STAB D xysp STAB oprx16 xysp DIR EXT IDX IDX1 IDX2 D IDX IDX2 5B dd 7B hh ll 6B xb 6B xb ff 6B xb ee ff 6B xb 6B ...

Page 248: ...d Execution Times STD Store Double Accumulator STD S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail STD opr8a STD opr16a STD oprx0_xysp STD oprx9 xysp STD oprx16 xysp STD D xysp STD oprx16 xysp DIR EXT IDX IDX1 IDX2 D IDX IDX2 5C dd 7C hh ll 6C xb 6C xb ff 6C xb ee ff 6C...

Page 249: ...he CPU to recover quickly when an inter rupt is used provided a stable clock is applied to the device If the system uses a clock reference crystal that also stops during low power mode crystal start up delay lengthens recovery time If XIRQ is asserted while the X mask bit 0 XIRQ interrupts enabled execution resumes with a vector fetch for the XIRQ interrupt If the X mask bit 1 XIRQ interrupts disa...

Page 250: ... one Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times STS Store Stack Pointer STS S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail STS opr8a STS opr16a STS oprx0_xysp STS oprx9 xysp STS oprx16 xysp STS D xysp STS oprx16 xysp DIR EXT ...

Page 251: ...ition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times STX Store Index Register X STX S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail STX opr8a STX opr16a STX oprx0_xysp STX oprx9 xysp STX oprx16 xysp STX D xysp STX oprx16 xysp DIR EXT IDX ID...

Page 252: ...ition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times STY Store Index Register Y STY S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 0000 cleared otherwise V 0 Cleared Source Form Address Mode Object Code Cycles Access Detail STY opr8a STY opr16a STY oprx0_xysp STY oprx9 xysp STY oprx16 xysp STY D xysp STY oprx16 xysp DIR EXT IDX ID...

Page 253: ...et cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if the value of the content of memory is larger than the value of the accumulator cleared otherwise Source Form Address Mode Object Code Cycles Access Detail SUBA opr8i SUBA opr8a SUBA opr16a SUBA oprx0_xysp SUBA o...

Page 254: ...et cleared otherwise Z Set if result is 00 cleared otherwise V X7 M7 R7 X7 M7 R7 Set if a two s complement overflow resulted from the operation cleared otherwise C X7 M7 M7 R7 R7 X7 Set if the value of the content of memory is larger than the value of the accumulator cleared otherwise Source Form Address Mode Object Code Cycles Access Detail SUBB opr8i SUBB opr8a SUBB opr16a SUBB oprx0_xysp SUBB o...

Page 255: ...ult is set cleared otherwise Z Set if result is 0000 cleared otherwise V D15 M15 R15 D15 M15 R15 Set if a two s complement overflow resulted from the operation cleared otherwise C D15 M15 M15 R15 R15 D15 Set if the value of the content of memory is larger than the value of the accumulator cleared otherwise Source Form Address Mode Object Code Cycles Access Detail SUBD opr16i SUBD opr8a SUBD opr16a...

Page 256: ...e CCR decrementing the SP before each item is stacked The I mask bit is then set the PC is loaded with the SWI vector and instruction ex ecution resumes at that location SWI is not affected by the I mask bit Refer to SECTION 7 EXCEPTION PROCESSING for more information Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times SWI Software Interrupt SWI S X H I N Z V C 1...

Page 257: ...ich does not affect condition codes the TAB instruction affects the N Z and V status bits for compatibility with M68HC11 Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times TAB Transfer from Accumulator A to Accumulator B TAB S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address M...

Page 258: ...LI WAI and CLI SEI This instruction is accomplished with the TFR A CCR instruction For compatibility with the M68HC11 the mnemonic TAP is translated by the assembler Condition Codes and Boolean Formulas Condition codes take on the value of the corresponding bit of accumu lator A except that the X mask bit cannot change from zero to one Software can leave the X bit set leave it cleared or change it...

Page 259: ...R B A which does not affect condition codes the TBA instruction affects N Z and V for compatibility with M68HC11 Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times TBA Transfer from Accumulator B to Accumulator A TBA S X H I N Z V C 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared Source Form Address Mode Obje...

Page 260: ...Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TBEQ Test and Branch if Equal to Zero TBEQ S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Encoding for lb is summarized in the following table Bit 3 is not used don t care bit 5 selects branch on zero TBEQ 0 or not zero TBNE 1 versions and bit 4 is the sign bit of the 9 bit relative ...

Page 261: ...nting the ratio XL X1 X2 X1 The 8 bit unrounded result is calculated using the following expression A Y1 B Y2 Y1 Where B XL X1 X2 X1 Y1 8 bit data entry pointed to by effective address Y2 8 bit data entry pointed to by effective address 1 The intermediate value B Y2 Y1 produces a 16 bit result with the radix point between bits 7 and 8 The result in A is the upper 8 bits inte ger part of this inter...

Page 262: ...Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TBNE Test and Branch if Not Equal to Zero TBNE S X H I N Z V C Source Form Address Mode Object Code1 Notes 1 Encoding for lb is summarized in the following table Bit 3 is not used don t care bit 5 selects branch on zero TBEQ 0 or not zero TBNE 1 versions and bit 4 is the sign bit of the 9 bit relat...

Page 263: ...an only be set by a reset or by recognition of an XIRQ interrupt Addressing Modes Machine Code and Execution Times TFR Transfer Register Content to Another Register TFR S X H I N Z V C or Source Form Address Mode Object Code1 Notes 1 Legal coding for eb is summarized in the following table Columns represent the high order digit and rows rep resent the low order digit in hexadecimal MSB is a don t ...

Page 264: ...mplemented by the TFR CCR A instruction For com patibility with the M68HC11 the mnemonic TPA is translated into the TFR CCR A instruction by the assembler Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TPA Transfer from Condition Code Register to Accumulator A TPA S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail TPA tra...

Page 265: ...AP uses the next address after the unimplemented opcode as a re turn address It stacks the return address index registers Y and X ac cumulators B and A and the CCR automatically decrementing the SP before each item is stacked The I mask bit is then set the PC is loaded with the trap vector and instruction execution resumes at that location This instruction is not maskable by the I bit Refer to SEC...

Page 266: ...er TST it performs the same function as BNE which is preferred After testing signed values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times TST Test Memory TST S X H I N Z V C 0 0 N Set if MSB of result is set cleared otherwise Z Set if result is 00 cleared otherwise V 0 Cleared C 0 Cleared Source Form Address Mode Object Code...

Page 267: ...gned value is less than zero BLO and BLS have no utility following TSTA While BHI can be used after TST it per forms the same function as BNE which is preferred After testing signed values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times TSTA Test A TSTA S X H I N Z V C 0 0 N Set if MSB of result is set cleared otherwise Z Set...

Page 268: ...gned value is less than zero BLO and BLS have no utility following TSTB While BHI can be used after TST it per forms the same function as BNE which is preferred After testing signed values all signed branches are available Condition Codes and Boolean Formulas Addressing Modes Machine Code and Execution Times TSTB Test B TSTB S X H I N Z V C 0 0 N Set if MSB of result is set cleared otherwise Z Set...

Page 269: ...nt of the SP remains unchanged After a TSX in struction X points at the last value that was stored on the stack Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TSX Transfer from Stack Pointer to Index Register X TSX S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail TSX translates to TFR SP X INH B7 75 1 P ...

Page 270: ...nt of the SP remains unchanged After a TSY in struction Y points at the last value that was stored on the stack Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TSY Transfer from Stack Pointer to Index Register Y TSY S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail TSY translates to TFR SP Y INH B7 76 1 P ...

Page 271: ...gister X value to the stack pointer The content of X is unchanged Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TXS Transfer from Index Register X to Stack Pointer TXS S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail TXS translates to TFR X SP INH B7 57 1 P ...

Page 272: ...gister Y value to the stack pointer The content of Y is unchanged Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times TYS Transfer from Index Register Y to Stack Pointer TYS S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail TYS translates to TFR Y SP INH B7 67 1 P ...

Page 273: ... can continue to run The CPU leaves the wait state when it sens es an interrupt that has not been masked Upon leaving the wait state the CPU sets the appropriate interrupt mask bit s fetches the vector corresponding to the interrupt sensed and in struction execution continues at the location the vector points to Condition Codes and Boolean Formulas Although the WAI instruction itself does not alte...

Page 274: ...at the final weighted average divide the content of Y D by X by executing an EDIV after the WAV This instruction can be interrupted If an interrupt occurs during WAV ex ecution the intermediate results six bytes are stacked in the order SOW 15 0 SOP 15 0 00 SOP 23 16 before the interrupt is processed The wavr pseudo instruction is used to resume execution after an inter rupt The mechanism is re en...

Page 275: ...ibility with the M68HC11 the XGDX instruction is translated into an EXG D X instruction by the assembler Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times XGDX Exchange Double Accumulator and Index Register X XGDX S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail XGDX translates to EXG D X INH B7 C5 1 P ...

Page 276: ...ibility with the M68HC11 the XGDY instruction is translated into an EXG D Y instruction by the assembler Condition Codes and Boolean Formulas None affected Addressing Modes Machine Code and Execution Times XGDY Exchange Double Accumulator and Index Register Y XGDY S X H I N Z V C Source Form Address Mode Object Code Cycles Access Detail XGDY translates to EXG D Y INH B7 C6 1 P ...

Page 277: ...e interrupts All vectors must be pro grammed to point to the address of the appropriate service routine The CPU12 can handle up to 64 exception vectors but the number actually used var ies from device to device and some vectors are reserved for Motorola use Refer to device documentation for more information Exceptions can be classified by the effect of the X and I interrupt mask bits on recog niti...

Page 278: ... these two exceptions have very low priority because any enabled interrupt source that is pending prior to the time exception pro cessing begins will take precedence However once the CPU begins processing a TRAP or SWI neither can be interrupted Also since these are mutually exclusive in structions they have no relative priority All remaining interrupts are subject to masking via the I bit in the ...

Page 279: ...g properly COP system to help protect against software failures When the COP is enabled software must write a particular code sequence to a specific address in order to keep a watchdog timer from timing out If software fails to execute the sequence properly a reset occurs 7 3 4 Clock Monitor Reset The clock monitor circuit uses an internal RC circuit to determine whether clock fre quency is above ...

Page 280: ... bits in control registers in addition to global masking by the I bit in the CCR Sources generally must be enabled by writing one or more bits in associated control registers There may be other interrupt related control bits and flags and there may be specific register read write sequences asso ciated with interrupt service Refer to individual on chip peripheral descriptions for de tails 7 4 3 Int...

Page 281: ...there If another interrupt is pending after registers are restored a new vector is fetched and the stack pointer is adjusted to point at the CCR value that was just recovered SP SP 9 This makes it appear that the registers have been stacked again After the SP is adjusted three program words are fetched to refill the instruction queue starting at the address the vector points to Processing then con...

Page 282: ...st cycle of all exception processing regardless of the cause is a vector fetch The vector points to the address where exception processing will continue Exception vectors are stored in a table located at the top of the memory map FFC0 FFFF The CPU cannot use the fetched vector until the third cycle of the exception process ing sequence During the vector fetch cycle the CPU issues a signal that tel...

Page 283: ...am word Finish filling instruction queue 3 2 P Fetch program word Start to fill instruction queue 4 2 S Push Y 6 2 P Fetch program word Continue to fill instruction queue 9 2 P Fetch program word Finish filling instruction queue 5 2 S Push X Transfer B A to 16 bit temp reg 7 2 S Push B A 8 2 s Push CCR byte Set I bit END 3 1 P Fetch program word Start to fill instruction queue 4 1 S Push Y 6 1 P F...

Page 284: ...on performed in cycle 8 1 Cycle 3 1 3 2 is the first of three program word fetches that refill the instruction queue Cycle 4 1 4 2 pushes Y onto the stack Cycle 5 1 5 2 pushes X onto the stack Cycle 6 1 6 2 is the second of three program word fetches that refill the instruction queue During this cycle the contents of the A and B accumulators are concatenated into a 16 bit word in the order B A Thi...

Page 285: ...e multiplexed information about data move ment in the queue and instruction execution To complete the picture for system de bugging it is also necessary to include program information and associated addresses in the reconstructed queue The instruction queue and cycle by cycle activity can be reconstructed in real time or from trace history captured by a logic analyzer However neither scheme can be...

Page 286: ... bus at the previous falling edge of E Execution information refers to the bus cycle from the current falling edge to the next falling edge of E Table 8 1 summarizes the information encoded on the IPIPE 1 0 pins Figure 8 1 Queue Status Signal Timing Table 8 1 IPIPE 1 0 Decoding Data Movement capture at E rise Mnemonic Meaning 0 0 No movement 0 1 LAT Latch data from bus 1 0 ALD Advance queue and lo...

Page 287: ... one word and stage 1 is refilled with a word of program information from the buffer The information was latched from the data bus at the falling edge of a previous E cycle because the instruction queue was not ready to advance when it arrived 8 2 5 INT Interrupt Sequence Encoding 0 1 The E cycle starting at this E fall is the first cycle of an interrupt sequence Normally this cycle is a read of t...

Page 288: ...han a single 16 bit access so the CPU sees only 16 bit words of program information To recover the 16 bit pro gram words externally latch the data bus state at the falling edge of E when ADDR0 0 and gate the outputs of the latch onto DATA 15 8 when a LAT or ALD cycle occurs Since the 8 bit data bus is connected to DATA 7 0 the 16 bit word on the data lines corresponds to the ALD or LAT status indi...

Page 289: ...ycle sequence VfPPP during which the reset vector is fetched and the instruction queue is filled before execution of the first instruction begins Due to the timing of the switchover of the IPIPE 1 0 pins from their alternate function as mode select inputs the status information on these two pins may be erroneous during the first cycle or two after the release of reset This is not a prob lem becaus...

Page 290: ...plemented with on chip hardware rather than external software and provides a full set of debug ging options The debugging system is less intrusive than systems used on other mi crocontrollers because the control logic resides in the on chip integration module rather than in the CPU Some activities such as reading and writing memory locations can be performed while the CPU is executing normal code ...

Page 291: ...heme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time This falling edge must be sent for every bit whether data is transmitted or received BKGD is an open drain pin that can be driven either by the MCU or by an external host Data is transferred MSB first at 16 E clock cycles per bit The interface times out if 512 E clock cycles occur betwee...

Page 292: ... low drive before the target begins to drive the active high speed up pulse seven cycles after the start of the bit time The host should sample the bit level about ten cycles after the start of bit time Figure 8 3 BDM Target to Host Serial Bit Timing Logic 1 10 CYCLES ECLOCK TARGET MCU HOST TRANSMIT 1 TARGET SENSES BIT EARLIEST START OF NEXT BIT SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT T...

Page 293: ...ter starting the bit time Figure 8 4 BDM Target to Host Serial Bit Timing Logic 0 8 4 3 BDM Commands All BDM opcodes are eight bits long and can be followed by an address or data as indicated by the instruction Commands implemented in BDM control hardware are listed in Table 8 2 These com mands except for BACKGROUND do not require the CPU to be in BDM mode for ex ecution The control logic uses CPU...

Page 294: ...allowed FF01 1100 0000 out READ_BD_BYTE FF01 Background mode active waiting for single wire serial command READ_BD_WORD EC 16 bit address 16 bit data out Read from memory with BDM in map may steal cycles if external access must be aligned access READ_BYTE E0 16 bit address 16 bit data out Read from memory with BDM out of map may steal cy cles if external access data for odd address on low byte dat...

Page 295: ...not be written during BDM operation Table 8 3 BDM Firmware Commands Command Opcode Hex Data Description GO 08 none Resume normal processing TRACE1 10 none Execute one user instruction then return to BDM TAGGO 18 none Enable tagging then resume normal processing WRITE_NEXT 42 16 bit data in X X 2 Write next word 0 X WRITE_PC 43 16 bit data in Write program counter WRITE_D 44 16 bit data in Write D ...

Page 296: ...d when BDM is entered Cleared by reset NOTE Execute a TAGGO command to enable instruction tagging Do not write ENTAG directly 0 Tagging not enabled or BDM active 1 Tagging active SDV Shifter Data Valid Shows that valid data is in the serial interface shift register NOTE SDV is used by firmware based instructions Do not attempt to write SDV directly 0 No valid data 1 Valid Data TRACE Trace Flag Sho...

Page 297: ...nal shares a pin with the LSTRB signal and the TAGHI signal shares a pin with the BKGD pin Tagging information is latched on the falling edge of ECLK as shown in Figure 8 5 Figure 8 5 Tag Input Timing Table 8 5 shows the functions of the two tagging pins The pins operate independent ly the state of one pin does not affect the function of the other The presence of logic level zero on either pin at ...

Page 298: ...set only on addresses When the breakpoint logic encounters the breakpoint tag the CPU12 executes an SWI instruction 2 Address only breakpoints that cause the MCU to enter BDM These break points can be set only on addresses When the breakpoint logic encounters the breakpoint tag BDM is activated 3 Address data breakpoints that cause the MCU to enter BDM These break points can be set on an address o...

Page 299: ...r to resume execution where a breakpoint oc curred the control program must preserve the breakpoint address rather than use the incremented PC value The breakpoint logic generally uses match registers to determine when a break is tak en Registers can be used to match the high and low bytes of addresses for single and dual breakpoints to match data for single breakpoints or to do both functions Use...

Page 300: ...MOTOROLA DEVELOPMENT AND DEBUG SUPPORT CPU12 8 16 REFERENCE MANUAL ...

Page 301: ...ton output membership functions Other instructions that are useful for custom fuzzy logic programs include MINA EMIND MAXM EMAXM TBL ETBL and EMACS For higher resolution fuzzy pro grams the fast extended precision math instructions in the CPU12 are also beneficial Flexible indexed addressing modes help simplify access to fuzzy logic data structures stored as lists or tabular data structures in mem...

Page 302: ... fuzzy inference kernel which is executed periodically to determine system outputs based on current system inputs The second part of the system is a knowledge base which contains membership functions and rules Figure 9 1 is a block diagram of this kind of fuzzy logic system The knowledge base can be developed by an application expert without any microcon troller programming experience Membership f...

Page 303: ... input The x axis of all three membership functions represents the range of possible values of the system input The vertical line through all three membership functions represents a specific system input value The y axis represents degree of truth and varies from completely false 00 or 0 to completely true FF or 100 The y value where the vertical line intersects each of the membership functions is...

Page 304: ... input and both pointers are updated automatically to point to the locations associated with the next fuzzy input The MEM instruction takes care of ev erything except counting the number of labels per system input and loading the current value of any subsequent system inputs The end result of the fuzzification step is a table of fuzzy inputs representing current system conditions 00 80 FF 0 F 32 F...

Page 305: ...standable to the microcontroller would be difficult but it is actually simple to reduce the rule to a small list of memory pointers The left portion of the rule is a statement of input condi tions and the right portion of the rule is a statement of output actions The left portion of a rule is made up of one or more in this case two antecedents con nected by a fuzzy and operator Each antecedent exp...

Page 306: ...t the same fuzzy output the rule that is most true governs the value in the fuzzy output because the rules are connected by an implied fuzzy or In the case of rule weighting the truth value for a rule is determined as usual by finding the smallest rule antecedent Before applying this truth value to the consequents for the rule the value is multiplied by a fraction from zero rule disabled to one ru...

Page 307: ... labels The program assembles to 57 bytes It executes in about 54 µs at an 8 MHz bus rate The basic structure can easily be extended to a general purpose system with a larger number of inputs and outputs Lines 1 to 3 set up pointers and load the system input value into the A accumulator Line 4 sets the loop count for the loop in lines 5 and 6 Lines 5 and 6 make up the fuzzification loop for seven ...

Page 308: ... consequents Line 17 is the REV instruction a self contained loop to process successive elements in the rule list until an FF character is found For a system of 17 rules with two ante cedents and one consequent each the REV instruction takes 259 cycles but it is in terruptible so it does not cause a long interrupt latency 01 2 FUZZIFY LDX INPUT_MFS Point at MF definitions 02 2 LDY FUZ_INS Point at...

Page 309: ... 1 Membership Function Definitions Figure 9 4 shows how a normal membership function is specified in the CPU12 Typ ically a software tool is used to input membership functions graphically and the tool generates data structures for the target processor and software kernel Alternatively points and slopes for the membership functions can be determined and stored in memory with define constant assembl...

Page 310: ...ship functions are evaluated Figure 9 5 is a complete flow diagram for the execution of a MEM instruction Each rectangular box represents one CPU bus cycle The number in the upper left corner corresponds to the cycle number and the letter corresponds to the cycle type refer to SECTION 6 INSTRUCTION GLOSSARY for details The up per portion of the box includes information about bus activity during th...

Page 311: ...he resulting grade should be FF as far as the right sloping side is concerned 4a decides if the value is left of the right sloping side Grade FF or on the sloping portion of the right side of the trapezoid Grade Grade_2 4b could still override this tentative value in grade 1 R Read word 0 X Point_1 and Point_2 2 R Read word 2 X Slope_1 and Slope_2 2a Delta_1 ACCA Point_1 2b Delta_2 Point_2 ACCA 2c...

Page 312: ...hese unusual cases The results are not all intuitively obvious but rather fall out from the specific al gorithm Remember these cases should not occur in a normal system 9 4 2 1 Abnormal Membership Function Case 1 This membership function is abnormal because the sloping sides cross below the FF cutoff level The flag_d12n signal forces the membership function to evaluate to 00 everywhere except from...

Page 313: ... case 3 is abnormal because the sloping sides cross below the FF cutoff level and the left sloping side has infinite slope In this case 4a is not true so grade equals grade_2 4b is true because slope_1 is zero so 4b does not overwrite grade Figure 9 8 Abnormal Membership Function Case 3 9 5 REV REVW Instruction Details This section provides a more detailed explanation of the rule evaluation instru...

Page 314: ...e er roneous The X index register is set to the address of the first element in the rule list in the knowledge base The REV instruction automatically updates this pointer so that the instruction can resume correctly if it is interrupted After the REV instruction finishes X will point at the next address past the FF separator character that marks the end of the rule list The Y index register is set...

Page 315: ...isters are stacked and the interrupt is hon ored When the interrupt service routine finishes an RTI instruction causes the CPU to recover its previous context from the stack and the REV instruction is resumed as if it had not been interrupted The stacked value of the program counter PC in case of an interrupted REV instruc tion points to the REV instruction rather than the instruction that follows...

Page 316: ... Rx FF other FF Other X X 1 point at next rule element 6 2 f No bus access Adjust X X 1 Continue to interrupt stacking V bit 0 min 1 max 6 0 x No bus access If Rx FE then A min A Fy 6 1 x If Rx FE or FF and ACCA Fy then Write byte Rx Y else no bus access Rx FF end of rules Yes No 7 0 O Read program word if 3A misaligned 3 0 f No bus access If Rx FE V was 1 Reset ACCA to FF If Rx FE Toggle V bit el...

Page 317: ... a read of any byte in the rule list The X index register is incremented so it points to the next element in the rule list Cycle 3 0 is needed to satisfy the required delay between a read and when data is valid to the CPU Some internal CPU housekeeping activity takes place during this cycle but there is no bus activity By cycle 4 0 the rule element that was read in cycle 2 0 is available to the CP...

Page 318: ...le byte needs to be re fetched when the REV instruction resumes After cycle 6 2 the REV instruction is finished and execution would continue to the normal interrupt processing flow 9 5 2 Weighted Rule Evaluation REVW This instruction implements a weighted variation of min max rule evaluation The weighting factors are stored in a table with one 8 bit entry per rule The weight is used to multiply th...

Page 319: ...n 8 bit weighting factor to represent a value between zero and one inclusive The 8 bit A accumulator is used to hold intermediate calculation results during execu tion of the REVW instruction During antecedent processing A starts out at FF and is replaced by any smaller fuzzy input that is referenced by a rule antecedent If rule weights are enabled by the C condition code bit equal one the rule tr...

Page 320: ...W instruction upon return from the inter rupt Since the CPU registers including the C bit and V bit in the condition codes reg ister indicate the current status of the interrupted REVW instruction this effectively causes the rule evaluation operation to resume from where it left off 9 5 2 3 Cycle by Cycle Details for REVW The central element of the REVW instruction is a three cycle loop that is ex...

Page 321: ...P2 5 3 f Adjust PC to point at current REVW instruction If Rx FFFF X0 X X X0 2 Min max mul max mul min V 1 V C 1 Rx FFFE or default 7 2 R Read rule word X0 Continue multiply 8 2 f No bus access Finish multiply 6 2 f No bus access Begin multiply of wt 1 A A B Rx FFFE or FFFF 6 1 x If A FRx write A to Rx else no bus access Adjust PC to point at next instruction If C 1 weights enabled Y TMP2 1 then r...

Page 322: ...he next loop pass The actual multiply takes place in cycles 6 2 through 8 2 The 8 bit weight from memory is incremented possibly over flowing to 100 before the multiply and the upper eight bits of the 16 bit internal result is used as the weighted result By using weight 1 the result can range from 0 0 times A to 1 0 times A After 8 2 flow continues to the next loop pass at cycle 4 0 At cycle 4 0 i...

Page 323: ...ex registers X and Y and accumulator B must be set up Index register X is a pointer to the Si singleton list X must have the address of the first singleton value in the knowledge base Index register Y is a pointer to the fuzzy outputs Fi Y must have the address of the first fuzzy output for this system output B is the iteration count n The B accumulator must be set to the number of la bels for thi...

Page 324: ...TMP1 By keeping these sums inside the CPU bus accesses are reduced and the WAV operation is optimized for high speed Cycles 4 0 through 11 0 form the eight cycle main loop for WAV The value in the 8 bit B accumulator is used to count the number of loop iterations B is decremented at the top of the loop in cycle 4 0 and the test for zero is located at the bottom of the loop after cycle 11 0 Cycle 5...

Page 325: ...SP SP 2 8 1 S Write word 2 SP stack TMP2 SP SP 2 9 1 S Write word 2 SP stack TMP3 SP SP 2 wavr 2 0 f No bus access 3 0 f No bus access TMP1 TMP2 TMP3 0000 4 0 f No bus access B B 1 decrement iteration counter Continue to interrupt stacking B 0 No Yes 5 0 r Read byte 0 Y fuzzy output Fi Y Y 1 point at next fuzzy output 6 0 r Read byte 0 X singleton Si X X 1 point at next singleton 7 0 f No bus acce...

Page 326: ... described above are suitable for a broad range of applications but some systems may require customization The built in fuzzy instructions use 8 bit resolution and some systems may require finer resolution The rule evaluation instructions only support variations of MIN MAX rule evaluation and other methods have been discussed in fuzzy logic literature The weighted average of singletons is not the ...

Page 327: ...y val ue for each of the resulting 257 endpoints The 16 bit D accumulator is then used as the x input to the table The upper eight bits A is used as a coarse lookup to find the line segment of interest and the lower eight bits B is used to interpolate within this line segment In the program sequence LDX TBL_START LDD DATA_IN TBL A X The notation A X causes the TBL instruction to use the Ath line s...

Page 328: ...p func tion shape is that there is a gradual transition from non membership to membership as the system input value approaches the central range of the membership function Let us examine the human problem of stopping a car at an intersection We might use rules like If intersection is close and speed is fast apply brakes The meaning re flected in membership function shape and position of the labels...

Page 329: ...erands The D at the end of the mnemonic stands for the D accumulator which is both the first operand for the com parison and the destination of the result The 2 X is an indexed addressing specifica tion that says X points to the second operand for the comparison When processing rule consequents the operand in the accumulator must remain con stant in case there is more than one consequent in the ru...

Page 330: ...ructions The weighted average of singletons is the most commonly used technique in micro controllers because it is computationally less difficult than most other methods The simplest method is called max defuzzification which simply uses the largest fuzzy out put as the system result However this approach does not take into account any other fuzzy outputs even when they are almost as true as the c...

Page 331: ...head to change banks and the need to disable interrupts while banks are switched The M68HC12 system requires no external glue logic Bank switching overhead is re duced by implementing control logic in the MCU Interrupts do not need to be disabled during switching because switching tasks are incorporated in special instructions that greatly simplify program access to extended memory Operation of th...

Page 332: ...d memory The upper 16 Kbyte block of memory space C000 FFFF is unpaged It is recommended that all reset and interrupt vectors point to locations in this area Although internal MCU resources such as control registers and on chip memory have default addresses out of reset each can typically be relocated by changing the default values in control registers Normally I O addresses control registers vect...

Page 333: ...any address in memory to any other address This is a big improvement over other bank switching schemes where the page switch operation can only be performed by a program outside the overlay window For all practical purposes the PPAGE value supplied by the instruction can be consid ered to be part of the effective address For all addressing mode variations except in dexed indirect modes the new pag...

Page 334: ... select registers onto the high order address lines when there is an ac cess to an address in a corresponding expansion window Assume that a device has six expansion address lines and an 8 bit PPAGE register The lines and the program expansion window have been enabled The address 9000 is within the 16 Kbyte program overlay window When there is an access to this ad dress the value in the PPAGE regi...

Page 335: ...a number of options that make it possible to use more than one range of addresses for matches as well as to enable various types and configurations of external devices Chip select circuits used in conjunction with the memory expansion scheme must be able to match all accesses made to addresses within the appropriate program overlay window In the case of the program expansion window the range of ad...

Page 336: ...TRP1A STRP1B Control Field These two bits program an extra delay into accesses to the CSP1 area of memory The choices are 0 1 2 or 3 E cycles in addition to the normal one cycle for un stretched accesses This allows use of slow external memory without slowing down the entire system When enabled CSP0 is active for the memory space from 8000 through FFFF This includes the program overlay space 8000 ...

Page 337: ...y The choices are 0 1 2 or 3 E cycles in addition to the normal one cycle for unstretched accesses This allows use of slow external memory without slowing down the entire system To use CSE with the extra overlay window it must be enabled CSEE 1 and con figured to follow the extra page CSEEP 1 10 6 System Notes The expansion overlay windows are specialized for specific application uses but there ar...

Page 338: ...MOTOROLA MEMORY EXPANSION CPU12 10 8 REFERENCE MANUAL ...

Page 339: ... the notation used in in struction glossary entries Table A 3 presents the same information in two digit hexa decimal format The first digit of the postbyte is represented by the value of the columns in the table The second digit of the postbyte is represented by the value of the row A 4 Transfer and Exchange Postbyte Encoding Table A 4 shows postbyte encoding for transfer and exchange instruction...

Page 340: ...3 3 4 6 6 ADCB opr B M C B Add with Carry to B IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 C9 ii D9 dd F9 hh ll E9 xb E9 xb ff E9 xb ee ff E9 xb E9 xb ee ff 1 3 3 3 3 4 6 6 ADDA opr A M A Add without Carry to A IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 8B ii 9B dd BB hh ll AB xb AB xb ff AB xb ee ff AB xb AB xb ee ff 1 3 3 3 3 4 6 6 ADDB opr B M B Add without Carry to B IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CB...

Page 341: ...R opr ASRA ASRB Arithmetic Shift Right Arithmetic Shift Right Accumulator A Arithmetic Shift Right Accumulator B EXT IDX IDX1 IDX2 D IDX IDX2 INH INH 77 hh ll 67 xb 67 xb ff 67 xb ee ff 67 xb 67 xb ee ff 47 57 4 3 4 5 6 6 1 1 BCC rel Branch if Carry Clear if C 0 REL 24 rr 3 1 BCLR opr msk M mm M Clear Bit s in Memory DIR EXT IDX IDX1 IDX2 4D dd mm 1D hh ll mm 0D xb mm 0D xb ff mm 0D xb ee ff mm 4 ...

Page 342: ... signed REL 2D rr 3 1 BMI rel Branch if Minus if N 1 REL 2B rr 3 1 BNE rel Branch if Not Equal if Z 0 REL 26 rr 3 1 BPL rel Branch if Plus if N 0 REL 2A rr 3 1 BRA rel Branch Always if 1 1 REL 20 rr 3 BRCLR opr msk rel Branch if M mm 0 if All Selected Bit s Clear DIR EXT IDX IDX1 IDX2 4F dd mm rr 1F hh ll mm rr 0F xb mm rr 0F xb ff mm rr 0F xb ee ff mm rr 4 5 4 6 8 BRN rel Branch Never if 1 0 REL ...

Page 343: ...7 2 CLC 0 C Translates to ANDCC FE IMM 10 FE 1 0 CLI 0 I Translates to ANDCC EF enables I bit interrupts IMM 10 EF 1 0 CLR opr CLRA CLRB 0 M Clear Memory Location 0 A Clear Accumulator A 0 B Clear Accumulator B EXT IDX IDX1 IDX2 D IDX IDX2 INH INH 79 hh ll 69 xb 69 xb ff 69 xb ee ff 69 xb 69 xb ee ff 87 C7 3 2 3 3 5 5 1 1 0 1 0 0 CLV 0 V Translates to ANDCC FD IMM 10 FD 1 0 CMPA opr A M Compare Ac...

Page 344: ...3 3 4 6 6 CPX opr X M M 1 Compare X to Memory 16 Bit IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 8E jj kk 9E dd BE hh ll AE xb AE xb ff AE xb ee ff AE xb AE xb ee ff 2 3 3 3 3 4 6 6 CPY opr Y M M 1 Compare Y to Memory 16 Bit IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 8D jj kk 9D dd BD hh ll AD xb AD xb ff AD xb ee ff AD xb AD xb ee ff 2 3 3 3 3 4 6 6 DAA Adjust Sum to BCD Decimal Adjust Accumulator A INH 18 07...

Page 345: ...D M M 1 IDX IDX1 IDX2 D IDX IDX2 18 1A xb 18 1A xb ff 18 1A xb ee ff 18 1A xb 18 1A xb ee ff 4 4 5 7 7 EMAXM opr MAX D M M 1 M M 1 MAX of 2 Unsigned 16 Bit Values N Z V and C status bits reflect result of internal compare D M M 1 IDX IDX1 IDX2 D IDX IDX2 18 1E xb 18 1E xb ff 18 1E xb ee ff 18 1E xb 18 1E xb ee ff 4 5 6 7 7 EMIND opr MIN D M M 1 D MIN of 2 Unsigned 16 Bit Values N Z V and C status ...

Page 346: ...allowed IDX 18 3F xb 10 EXG r1 r2 r1 r2 if r1 and r2 same size or 00 r1 r2 if r1 8 bit r2 16 bit or r1low r2 if r1 16 bit r2 8 bit r1 and r2 may be A B CCR D X Y or SP INH B7 eb 1 FDIV D X X r D 16 16 Bit Fractional Divide INH 18 11 12 IBEQ cntr rel cntr 1 cntr If cntr 0 then Branch else Continue to next instruction Increment Counter and Branch if 0 cntr A B D X Y or SP REL 9 bit 04 lb rr 3 IBNE c...

Page 347: ...25 qq rr 4 3 LBEQ rel Long Branch if Equal if Z 1 REL 18 27 qq rr 4 3 LBGE rel Long Branch Greater Than or Equal if N V 0 signed REL 18 2C qq rr 4 3 LBGT rel Long Branch if Greater Than if Z N V 0 signed REL 18 2E qq rr 4 3 LBHI rel Long Branch if Higher if C Z 0 unsigned REL 18 22 qq rr 4 3 LBHS rel Long Branch if Higher or Same if C 0 unsigned same function as LBCC REL 18 24 qq rr 4 3 LBLE rel L...

Page 348: ... IDX IDX1 IDX2 D IDX IDX2 CC jj kk DC dd FC hh ll EC xb EC xb ff EC xb ee ff EC xb EC xb ee ff 2 3 3 3 3 4 6 6 0 LDS opr M M 1 SP Load Stack Pointer IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CF jj kk DF dd FF hh ll EF xb EF xb ff EF xb ee ff EF xb EF xb ee ff 2 3 3 3 3 4 6 6 0 LDX opr M M 1 X Load Index Register X IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 CE jj kk DE dd FE hh ll EE xb EE xb ff EE xb ee ff E...

Page 349: ...xb ee ff 44 54 4 3 4 5 6 6 1 1 0 LSRD Logical Shift Right D Accumulator INH 49 1 0 MAXA MAX A M A MAX of 2 Unsigned 8 Bit Values N Z V and C status bits reflect result of internal compare A M IDX IDX1 IDX2 D IDX IDX2 18 18 xb 18 18 xb ff 18 18 xb ee ff 18 18 xb 18 18 xb ee ff 4 4 5 7 7 MAXM MAX A M M MAX of 2 Unsigned 8 Bit Values N Z V and C status bits reflect result of internal compare A M IDX ...

Page 350: ...EXT EXT IDX IDX EXT IDX IDX 18 03 jj kk hh ll 18 00 xb jj kk 18 04 hh ll hh ll 18 01 xb hh ll 18 05 xb hh ll 18 02 xb xb 5 4 6 5 5 5 MUL A B A B 8 8 Unsigned Multiply INH 12 3 NEG opr NEGA NEGB 0 M M or M 1 M Two s Complement Negate 0 A A equivalent to A 1 B Negate Accumulator A 0 B B equivalent to B 1 B Negate Accumulator B EXT IDX IDX1 IDX2 D IDX IDX2 INH INH 70 hh ll 60 xb 60 xb ff 60 xb ee ff ...

Page 351: ... PULC M SP CCR SP 1 SP Pull CCR from Stack INH 38 3 PULD M SP M SP 1 A B SP 2 SP Pull D from Stack INH 3A 3 PULX M SP M SP 1 XH XL SP 2 SP Pull Index Register X from Stack INH 30 3 PULY M SP M SP 1 YH YL SP 2 SP Pull Index Register Y from Stack INH 31 3 REV MIN MAX rule evaluation Find smallest rule input MIN Store to rule outputs unless fuzzy output is already larger MAX For rule weights see REVW...

Page 352: ...IDX1 IDX2 D IDX IDX2 INH INH 75 hh ll 65 xb 65 xb ff 65 xb ee ff 65 xb 65 xb ee ff 45 55 4 3 4 5 6 6 1 1 ROR opr RORA RORB Rotate Memory Right through Carry Rotate A Right through Carry Rotate B Right through Carry EXT IDX IDX1 IDX2 D IDX IDX2 INH INH 76 hh ll 66 xb 66 xb ff 66 xb ee ff 66 xb 66 xb ee ff 46 56 4 3 4 5 6 6 1 1 RTC M SP PPAGE SP 1 SP M SP M SP 1 PCH PCL SP 2 SP Return from Call INH ...

Page 353: ... r2 00 r1 r2 if r1 bit 7 is 0 or FF r1 r2 if r1 bit 7 is 1 Sign Extend 8 bit r1 to 16 bit r2 r1 may be A B or CCR r2 may be D X Y or SP Alternate mnemonic for TFR r1 r2 INH B7 eb 1 STAA opr A M Store Accumulator A to Memory DIR EXT IDX IDX1 IDX2 D IDX IDX2 5A dd 7A hh ll 6A xb 6A xb ff 6A xb ee ff 6A xb 6A xb ee ff 2 3 2 3 3 5 5 0 STAB opr B M Store Accumulator B to Memory DIR EXT IDX IDX1 IDX2 D ...

Page 354: ... Store Index Register X DIR EXT IDX IDX1 IDX2 D IDX IDX2 5E dd 7E hh ll 6E xb 6E xb ff 6E xb ee ff 6E xb 6E xb ee ff 2 3 2 3 3 5 5 0 STY opr YH YL M M 1 Store Index Register Y DIR EXT IDX IDX1 IDX2 D IDX IDX2 5D dd 7D hh ll 6D xb 6D xb ff 6D xb ee ff 6D xb 6D xb ee ff 2 3 2 3 3 5 5 0 SUBA opr A M A Subtract Memory from Accumulator A IMM DIR EXT IDX IDX1 IDX2 D IDX IDX2 80 ii 90 dd B0 hh ll A0 xb A...

Page 355: ... else Continue to next instruction Test Counter and Branch if Zero cntr A B D X Y or SP REL 9 bit 04 lb rr 3 TBL opr M B M 1 M A 8 Bit Table Lookup and Interpolate Initialize B and index before TBL ea points at first 8 bit table entry M and B is fractional part of lookup value no indirect addressing modes allowed IDX 18 3D xb 8 TBNE cntr rel If cntr not 0 then Branch else Continue to next instruct...

Page 356: ... Y INH B7 76 1 TXS X SP Translates to TFR X SP INH B7 57 1 TYS Y SP Translates to TFR Y SP INH B7 67 1 WAI SP 2 SP RTNH RTNL M SP M SP 1 SP 2 SP YH YL M SP M SP 1 SP 2 SP XH XL M SP M SP 1 SP 2 SP B A M SP M SP 1 SP 1 SP CCR M SP WAIT for interrupt INH 3E 8 in 5 int or or 1 1 1 WAV Calculate Sum of Products and Sum of Weights for Weighted Average Calculation Initialize B X and Y before WAV B speci...

Page 357: ...do instruction see WAV Resume executing an interrupted WAV in struction recover intermediate results from stack rather than initializing them to zero Special 3C XGDX D X Translates to EXG D X INH B7 C5 1 XGDY D Y Translates to EXG D Y INH B7 C6 1 NOTES Each cycle is typically 125 ns for an 8 MHz bus 16 MHz oscillator Refer to detailed instruction descriptions for additional information Table A 1 I...

Page 358: ... 6 ASR ID 2 4 77 4 ASR EX 3 87 1 CLRA IH 1 97 1 TSTA IH 1 A7 1 NOP IH 1 B7 1 TFR EXG IH 2 C7 1 CLRB IH 1 D7 1 TSTB IH 1 E7 3 6 TST ID 2 4 F7 3 TST EX 3 08 1 INX IH 1 18 page 2 28 3 1 BVC RL 2 38 3 PULC IH 1 48 1 ASLA IH 1 58 1 ASLB IH 1 68 3 6 ASL ID 2 4 78 4 ASL EX 3 88 1 EORA IM 2 98 3 EORA DI 2 A8 3 6 EORA ID 2 4 B8 3 EORA EX 3 C8 1 EORB IM 2 D8 3 EORB DI 2 E8 3 6 EORB ID 2 4 F8 3 EORB EX 3 09 ...

Page 359: ...0 TRAP IH 2 67 10 TRAP IH 2 77 10 TRAP IH 2 87 10 TRAP IH 2 97 10 TRAP IH 2 A7 10 TRAP IH 2 B7 10 TRAP IH 2 C7 10 TRAP IH 2 D7 10 TRAP IH 2 E7 10 TRAP IH 2 F7 10 TRAP IH 2 08 4 MOVB IM ID 4 18 4 7 MAXA ID 3 5 28 4 3 LBVC RL 4 38 10 TRAP IH 2 48 10 TRAP IH 2 58 10 TRAP IH 2 68 10 TRAP IH 2 78 10 TRAP IH 2 88 10 TRAP IH 2 98 10 TRAP IH 2 A8 10 TRAP IH 2 B8 10 TRAP IH 2 C8 10 TRAP IH 2 D8 10 TRAP IH ...

Page 360: ...e inc 77 8 Y post inc 87 7 SP 5b const 97 9 SP 5b const A7 8 SP pre inc B7 8 SP post inc C7 7 PC 5b const D7 9 PC 5b const E7 D X D indirect F7 D SP D indirect 08 8 X 5b const 18 8 X 5b const 28 8 X pre dec 38 8 X post dec 48 8 Y 5b const 58 8 Y 5b const 68 8 Y pre dec 78 8 Y post dec 88 8 SP 5b const 98 8 SP 5b const A8 8 SP pre dec B8 8 SP post dec C8 8 PC 5b const D8 8 PC 5b const E8 n Y 9b con...

Page 361: ...TMP3 Y D Y X Y Y Y SP Y 7 sex A SP SEX A SP sex B SP SEX B SP sex CCR SP SEX CCR SP TMP3 SP D SP X SP Y SP SP SP EXCHANGES LS MS 8 9 A B C D E F 0 A A B A CCR A TMP3L A 00 A TMP3 B A A B XL A 00 A X YL A 00 A Y SPL A 00 A SP 1 A B B B CCR B TMP3L B FF B TMP3 B B FF A XL B FF B X YL B FF B Y SPL B FF B SP 2 A CCR B CCR CCR CCR TMP3L CCR FF CCR TMP3 B CCR FF CCR D XL CCR FF CCR X YL CCR FF CCR Y SPL...

Page 362: ... see below rr can specify X Y SP or PC 111rr011 n r 16 bit offset indexed indirect rr can specify X Y SP or PC rr1pnnnn n r n r n r n r Auto pre decrement increment or Auto post decrement increment p pre 0 or post 1 n 8 to 1 1 to 8 rr can specify X Y or SP PC not a valid choice 111rr1aa A r B r D r Accumulator offset unsigned 8 bit or 16 bit aa 00 A 01 B 10 D 16 bit 11 see accumulator D offset ind...

Page 363: ...14 D DBEQ 24 D DBNE 34 D DBNE 44 D TBEQ 54 D TBEQ 64 D TBNE 74 D TBNE 84 D IBEQ 94 D IBEQ A4 D IBNE B4 D IBNE 05 X DBEQ 15 X DBEQ 25 X DBNE 35 X DBNE 45 X TBEQ 55 X TBEQ 65 X TBNE 75 X TBNE 85 X IBEQ 95 X IBEQ A5 X IBNE B5 X IBNE 06 Y DBEQ 16 Y DBEQ 26 Y DBNE 36 Y DBNE 46 Y TBEQ 56 Y TBEQ 66 Y TBNE 76 Y TBNE 86 Y IBEQ 96 Y IBEQ A6 Y IBNE B6 Y IBNE 07 SP DBEQ 17 SP DBEQ 27 SP DBNE 37 SP DBNE 47 SP ...

Page 364: ...MOTOROLA INSTRUCTION REFERENCE CPU12 A 26 REFERENCE MANUAL ...

Page 365: ...PU12 instructions affect condition code bits in the same way as M68HC11 instructions CPU12 object code is similar to but not identical to M68HC11 object code Some pri mary objectives such as the elimination of the penalty for using Y could not be achieved without object code differences While the object code has been changed the majority of the opcodes are identical to those of the M6800 which was...

Page 366: ... object code is six bytes smaller than the M68HC11 code It is fair to conclude that M68HC11 code can be reassembled with very little change in size Table B 1 Translated M68HC11 Mnemonics M68HC11 Mnemonic Equivalent CPU12 Instruction Comments ABX ABY LEAX B X LEAY B Y Since CPU12 has accumulator offset indexing ABX and ABY are rarely used in new CPU12 programs ABX was one byte on M68HC11 but ABY wa...

Page 367: ... these instructions were performed as sequences of 8 bit opera tions The CPU12 is a true 16 bit implementation but it retains the ability to work with the mostly 8 bit M68HC11 instruction set The larger ALU of the CPU12 it can per form some 20 bit operations is used to calculate 16 bit pointers and to speed up math operations Table B 2 Instructions with Smaller Object Code Instruction Comments DEY...

Page 368: ...the opcode in the low or der half of this word The instruction queue causes three bytes of program information starting with the in struction opcode to be directly available to the CPU at the beginning of every instruc tion As it executes each instruction performs enough additional program fetches to refill the space it took up in the queue Alignment information is maintained by the log ic in the ...

Page 369: ...upts Since this is an odd number of bytes there is no practical way to assure that the stack will stay aligned To assure that instructions take a fixed number of cycles regardless of stack alignment the internal RAM in M68HC12 MCUs is designed to allow single cycle 16 bit accesses to misaligned addresses As long as the stack is located in this special RAM stacking and unstacking operations take th...

Page 370: ...nded ad dress To make an M68HC11 source program that contains such a sequence work on the CPU12 change either the initial LDS xxxx or the absolute extended ad dress used to read the stack B 5 Improved Indexing The CPU12 has significantly improved indexed addressing capability yet retains compatibility with the M68HC11 The one cycle and one byte cost of doing Y related indexing in the M68HC11 has b...

Page 371: ...riations of constant offset indexing in order to optimize the efficiency of object code generation The most common constant offset is zero Offsets of 1 2 4 are used fairly often but with less frequency than zero The 5 bit constant offset variation covers the most frequent indexing requirements by including the offset in the postbyte This reduces a load accumulator indexed instruc tion to two bytes...

Page 372: ...he page prebyte for each Y related instruction 18 CPU12 post increment indexing capability allowed the two INY instructions to be absorbed into the LDAA indexed instruction The replacement code is not identical to the original three instruction se quence because the Z condition code bit is affected by the M68HC11 INY instruc tions while the Z bit in the CPU12 would be determined by the value loade...

Page 373: ...ated using advanced semi conductor processing the same methods used to manufacture the M68HC16 and M68300 families of modular microcontrollers M68HC12 devices have a base bus speed of eight MHz and are designed to operate over a wide range of supply voltag es The 16 bit wide architecture also increases performance Beyond these obvious improvements the CPU12 uses a reduced number of cycles for many...

Page 374: ...gram for the CPU12 requires about 50 bytes The CPU12 fuzzy logic instructions replace whole subrou tines in the M68HC11 version Table lookup instructions also greatly reduce code space Other CPU12 code space reductions are more subtle Memory to memory moves are one example The CPU12 move instruction requires almost as many bytes as an equivalent sequence of M68HC11 instructions but the move operat...

Page 375: ...raphs discuss significant enhancements Table B 4 New M68HC12 Instructions Mnemonic Addressing Modes Brief Functional Description ANDCC Immediate AND CCR with Mask replaces CLC CLI and CLV BCLR Extended Bit s Clear added extended mode BGND Inherent Enter Background Debug Mode if enabled BRCLR Extended Branch if Bit s Clear added extended mode BRSET Extended Branch if Bit s Set added extended mode B...

Page 376: ...Maximum of Two Unsigned 8 Bit Values MAXM Indexed Maximum of Two Unsigned 8 Bit Values MEM Special Determine Grade of Fuzzy Membership MINA Indexed Minimum of Two Unsigned 8 Bit Values MINM Indexed Minimum of Two Unsigned 8 Bit Values MOVB W Combinations of Immediate Extended and Indexed Move Data from One Memory Location to Another ORCC Immediate OR CCR with Mask replaces SEC SEI and SEV PSHC Inh...

Page 377: ...hat can be used to transfer or exchange data between any two CPU registers The operation is obvious when the two registers are the same size but some of the other combinations provide very useful results For example when an 8 bit register is transferred to a 16 bit register a sign extend operation is performed Other combinations can be used to perform a zero extend operation These instructions are...

Page 378: ...re performed by executing a compare followed by a conditional branch around a load or store operation These instructions can also be used to limit a data value prior to using it as an input to a table lookup or other routine Suppose a table is valid for input values between 20 and 7F An arbitrary input value can be tested against these limits and be replaced by the largest legal value if it is too...

Page 379: ... value of the beginning point plus this signed interme diate delta y value B 7 8 Extended Bit Manipulation The M68HC11 CPU only allows direct or indexed addressing This typically causes the programmer to dedicate an index register to point at some memory area such as the on chip registers The CPU12 allows all bit manipulation instructions to work with direct extended or indexed addressing modes B ...

Page 380: ...mber is saved and restored automatically during execu tion Since the page change operation is part of an uninterruptable instruction many of the difficulties associated with bank switching are eliminated On M68HC12 deriva tives with expanded memory capability bank numbers are specified by on chip con trol registers Since the addresses of these control registers may not be the same in all M68HC12 d...

Page 381: ...n instructions which are available in extended direct and indexed variations The char data type is a sim ple 8 bit value that is commonly used to specify variables in a small microcontroller system because it requires less memory space than a 16 bit integer provided the vari able has a range small enough to fit into eight bits The 16 bit CPU12 can easily han dle 16 bit integer types and the availa...

Page 382: ...eight bytes worth of temporary storage Post increment indexed addressing is used in this example but all four combinations of pre post increment decrement are available offsets from 8 to 8 inclusive from X Y or SP This form of indexing can often be used to get an index or stack pointer adjustment for free during an indexed operation the instruction requires no more code space or cycles than a zero...

Page 383: ...a set of six basic loop control instructions which decrement in crement or test a loop count register and then branch if it is either equal to zero or not equal to zero The loop count register can be A B D X Y or SP A or B could be used if the loop count fits in an 8 bit char variable the other choices are all 16 bit registers The relative offset for the loop branch is a 9 bit signed value so thes...

Page 384: ...ndirect ad dressing to determine which path to take Depending upon the situation cases can use either the constant offset variation or the accumulator D offset variation of indirect indexed addressing C 7 Pointers The CPU12 supports pointers by allowing direct arithmetic operations on the 16 bit in dex registers LEAS LEAX and LEAY instructions and by allowing indexed indirect addressing modes C 8 ...

Page 385: ...ine is on the current page or in an area of memory that is always visible in the 64 Kbyte map regardless of the bank page selection Push and pull instructions can be used to stack some or all the CPU registers during a function call The CPU12 can push and pull any of the CPU registers A B CCR D X Y or SP C 9 Instruction Set Orthogonality One very helpful aspect of the CPU12 instruction set orthogo...

Page 386: ...MOTOROLA HIGH LEVEL LANGUAGE SUPPORT CPU12 C 6 REFERENCE MANUAL ...

Page 387: ... x d117 a9 40 adca y d119 a9 af adca 1 sp d11b a9 2f adca 1 x d11d a9 6f adca 1 y d11f a9 a8 adca 8 sp d121 a9 28 adca 8 x d123 a9 68 adca 8 y d125 a9 9f adca 1 sp d127 a9 1f adca 1 x d129 a9 5f adca 1 y d12b a9 90 adca 16 sp d12d a9 10 adca 16 x d12f a9 50 adca 16 y d131 a9 f1 ef adca 17 sp d134 a9 e1 ef adca 17 x d137 a9 e9 ef adca 17 y d13a a9 d2 adca small pc d13c a9 92 adca small sp d13e a9 1...

Page 388: ...5 asl dir d21d 78 01 88 asl ext d220 48 asla d221 58 aslb d222 59 asld d223 67 a0 asr 1 sp d225 77 00 55 asr dir d228 77 01 88 asr ext d22b 47 asra d22c 57 asrb d22d 24 fe bcc d22f 25 fe bcs d231 27 fe beq d233 2c fe bge d235 2e fe bgt d237 22 fe bhi d239 85 72 bita immed d23b a5 a0 bita 1 sp d23d 95 55 bita dir d23f b5 01 88 bita ext d242 c5 72 bitb immed d244 e5 a0 bitb 1 sp d246 d5 55 bitb dir ...

Page 389: ... 30 55 call 1 x 55 d394 4b 70 55 call 1 y 55 d397 4b 81 55 call 1 sp 55 d39a 4b 01 55 call 1 x 55 d39d 4b 41 55 call 1 y 55 d3a0 4b bf 55 call 1 sp 55 d3a3 4b 3f 55 call 1 x 55 d3a6 4b 7f 55 call 1 y 55 d3a9 4b f8 7d 55 call 125 pc 55 d3ad 4b f0 7d 55 call 125 sp 55 d3b1 4b e0 7d 55 call 125 x 55 d3b5 4b e8 7d 55 call 125 y 55 d3b9 4b 8f 55 call 15 sp 55 d3bc 4b 0f 55 call 15 x 55 d3bf 4b 4f 55 ca...

Page 390: ...dir d4e1 f1 01 88 cmpb ext d4e4 f1 01 88 cmpb ext d4e7 e1 f2 01 88 cmpb ext sp d4eb e1 e2 01 88 cmpb ext x d4ef e1 ea 01 88 cmpb ext y d4f3 e1 f8 37 cmpb ind pc d4f6 e1 f0 37 cmpb ind sp d4f9 e1 e0 37 cmpb ind x d4fc e1 e8 37 cmpb ind y d4ff e1 ce cmpb small pc d501 e1 8e cmpb small sp d503 e1 0e cmpb small x d505 e1 4e cmpb small y d507 61 a0 com 1 sp d509 61 20 com 1 x d50b 61 60 com 1 y d50d 61...

Page 391: ... sp d60f ac 30 cpd 1 x d611 ac 70 cpd 1 y d613 ac 81 cpd 1 sp d615 ac 01 cpd 1 x d617 ac 41 cpd 1 y d619 ac bf cpd 1 sp d61b ac 3f cpd 1 x d61d ac 7f cpd 1 y d61f ac f8 7d cpd 125 pc d622 ac f0 7d cpd 125 sp d625 ac e0 7d cpd 125 x d628 ac e8 7d cpd 125 y d62b ac 8f cpd 15 sp d62d ac 0f cpd 15 x d62f ac 4f cpd 15 y d631 ac f0 10 cpd 16 sp d634 ac e0 10 cpd 16 x d637 ac e8 10 cpd 16 y d63a ac b7 cp...

Page 392: ...af 4e cps small y d73f 8e 00 72 cpx immed d742 8e 00 72 cpx immed d745 ae a0 cpx 1 sp d747 ae 20 cpx 1 x d749 ae 60 cpx 1 y d74b ae a7 cpx 8 sp d74d ae 27 cpx 8 x d74f ae 67 cpx 8 y d751 ae c0 cpx pc d753 ae 80 cpx sp d755 ae 00 cpx x d757 ae 40 cpx y d759 ae af cpx 1 sp d75b ae 2f cpx 1 x d75d ae 6f cpx 1 y d75f ae a8 cpx 8 sp d761 ae 28 cpx 8 x d763 ae 68 cpx 8 y d765 ae 9f cpx 1 sp d767 ae 1f c...

Page 393: ... ad 8f cpy 15 sp d86a ad 0f cpy 15 x d86c ad 4f cpy 15 y d86e ad f0 10 cpy 16 sp d871 ad e0 10 cpy 16 x d874 ad e8 10 cpy 16 y d877 ad b7 cpy 8 sp d879 ad 37 cpy 8 x d87b ad 77 cpy 8 y d87d ad b8 cpy 8 sp d87f ad 38 cpy 8 x d881 ad 78 cpy 8 y d883 ad f4 cpy a sp d885 ad e4 cpy a x d887 ad ec cpy a y d889 ad f5 cpy b sp d88b ad e5 cpy b x d88d ad ed cpy b y d88f ad f6 cpy d sp d891 ad e6 cpy d x d8...

Page 394: ... 18 1a 00 emaxd x d9b6 18 1a 40 emaxd y d9b9 18 1a af emaxd 1 sp d9bc 18 1a 2f emaxd 1 x d9bf 18 1a 6f emaxd 1 y d9c2 18 1a a8 emaxd 8 sp d9c5 18 1a 28 emaxd 8 x d9c8 18 1a 68 emaxd 8 y d9cb 18 1a 9f emaxd 1 sp d9ce 18 1a 1f emaxd 1 x d9d1 18 1a 5f emaxd 1 y d9d4 18 1a 90 emaxd 16 sp d9d7 18 1a 10 emaxd 16 x d9da 18 1a 50 emaxd 16 y d9dd 18 1a f1 ef emaxd 17 sp d9e1 18 1a e1 ef emaxd 17 x d9e5 18 ...

Page 395: ... 1e 38 emaxm 8 x db4e 18 1e 78 emaxm 8 y db51 18 1e f4 emaxm a sp db54 18 1e e4 emaxm a x db57 18 1e ec emaxm a y db5a 18 1e f5 emaxm b sp db5d 18 1e e5 emaxm b x db60 18 1e ed emaxm b y db63 18 1e f6 emaxm d sp db66 18 1e e6 emaxm d x db69 18 1e ee emaxm d y db6c 18 1e f2 01 88 emaxm ext sp db71 18 1e e2 01 88 emaxm ext x db76 18 1e ea 01 88 emaxm ext y db7b 18 1e f8 37 emaxm ind pc db7f 18 1e f0...

Page 396: ...m 0 pc dcf2 18 1f 80 eminm 0 sp dcf5 18 1f 00 eminm 0 x dcf8 18 1f 40 eminm 0 y dcfb 18 1f b0 eminm 1 sp dcfe 18 1f 30 eminm 1 x dd01 18 1f 70 eminm 1 y dd04 18 1f 81 eminm 1 sp dd07 18 1f 01 eminm 1 x dd0a 18 1f 41 eminm 1 y dd0d 18 1f bf eminm 1 sp dd10 18 1f 3f eminm 1 x dd13 18 1f 7f eminm 1 y dd16 18 1f f8 7d eminm 125 pc dd1a 18 1f f0 7d eminm 125 sp dd1e 18 1f e0 7d eminm 125 x dd22 18 1f e...

Page 397: ...e eora small y de51 c8 72 eorb immed de53 c8 72 eorb immed de55 e8 a0 eorb 1 sp de57 e8 20 eorb 1 x de59 e8 60 eorb 1 y de5b e8 a7 eorb 8 sp de5d e8 27 eorb 8 x de5f e8 67 eorb 8 y de61 e8 c0 eorb pc de63 e8 80 eorb sp de65 e8 00 eorb x de67 e8 40 eorb y de69 e8 af eorb 1 sp de6b e8 2f eorb 1 x de6d e8 6f eorb 1 y de6f e8 a8 eorb 8 sp de71 e8 28 eorb 8 x de73 e8 68 eorb 8 y de75 e8 9f eorb 1 sp de...

Page 398: ... b7 e0 exg y a df70 b7 e1 exg y b df72 b7 e2 exg y ccr df74 b7 e4 exg y d df76 b7 e7 exg y sp df78 b7 e5 exg y x df7a b7 e6 exg y y df7c 18 11 fdiv df7e 18 10 idiv df80 62 a0 inc 1 sp df82 62 20 inc 1 x df84 62 60 inc 1 y df86 62 a7 inc 8 sp df88 62 27 inc 8 x df8a 62 67 inc 8 y df8c 62 c0 inc pc df8e 62 80 inc sp df90 62 00 inc x df92 62 40 inc y df94 62 af inc 1 sp df96 62 2f inc 1 x df98 62 6f ...

Page 399: ...92 05 3f jmp 1 x e094 05 7f jmp 1 y e096 05 f8 7d jmp 125 pc e099 05 f0 7d jmp 125 sp e09c 05 e0 7d jmp 125 x e09f 05 e8 7d jmp 125 y e0a2 05 8f jmp 15 sp e0a4 05 0f jmp 15 x e0a6 05 4f jmp 15 y e0a8 05 f0 10 jmp 16 sp e0ab 05 e0 10 jmp 16 x e0ae 05 e8 10 jmp 16 y e0b1 05 b7 jmp 8 sp e0b3 05 37 jmp 8 x e0b5 05 77 jmp 8 y e0b7 05 b8 jmp 8 sp e0b9 05 38 jmp 8 x e0bb 05 78 jmp 8 y e0bd 05 f4 jmp a sp...

Page 400: ... 18 2f ff fc lble e1d5 18 23 ff fc lbls e1d9 18 2d ff fc lblt e1dd 18 2b ff fc lbmi e1e1 18 26 ff fc lbne e1e5 18 2a ff fc lbpl e1e9 18 20 ff fc lbra e1ed 18 21 ff fc lbrn e1f1 15 fa ff fc lbsr e1f5 18 28 ff fc lbvc e1f9 18 29 ff fc lbvs e1fd 86 72 ldaa immed e1ff 86 72 ldaa immed e201 a6 a0 ldaa 1 sp e203 a6 20 ldaa 1 x e205 a6 60 ldaa 1 y e207 a6 a7 ldaa 8 sp e209 a6 27 ldaa 8 x e20b a6 67 ldaa ...

Page 401: ... ldab 1 x e308 e6 70 ldab 1 y e30a e6 81 ldab 1 sp e30c e6 01 ldab 1 x e30e e6 41 ldab 1 y e310 e6 bf ldab 1 sp e312 e6 3f ldab 1 x e314 e6 7f ldab 1 y e316 e6 f8 7d ldab 125 pc e319 e6 f0 7d ldab 125 sp e31c e6 e0 7d ldab 125 x e31f e6 e8 7d ldab 125 y e322 e6 8f ldab 15 sp e324 e6 0f ldab 15 x e326 e6 4f ldab 15 y e328 e6 f0 10 ldab 16 sp e32b e6 e0 10 ldab 16 x e32e e6 e8 10 ldab 16 y e331 e6 b...

Page 402: ...ldd small y e439 cf 00 72 lds immed e43c cf 00 72 lds immed e43f ef a0 lds 1 sp e441 ef 20 lds 1 x e443 ef 60 lds 1 y e445 ef a7 lds 8 sp e447 ef 27 lds 8 x e449 ef 67 lds 8 y e44b ef c0 lds pc e44d ef 80 lds sp e44f ef 00 lds x e451 ef 40 lds y e453 ef af lds 1 sp e455 ef 2f lds 1 x e457 ef 6f lds 1 y e459 ef a8 lds 8 sp e45b ef 28 lds 8 x e45d ef 68 lds 8 y e45f ef 9f lds 1 sp e461 ef 1f lds 1 x...

Page 403: ...x 15 y e563 ee f0 10 ldx 16 sp e566 ee e0 10 ldx 16 x e569 ee e8 10 ldx 16 y e56c ee b7 ldx 8 sp e56e ee 37 ldx 8 x e570 ee 77 ldx 8 y e572 ee b8 ldx 8 sp e574 ee 38 ldx 8 x e576 ee 78 ldx 8 y e578 ee f4 ldx a sp e57a ee e4 ldx a x e57c ee ec ldx a y e57e ee f5 ldx b sp e580 ee e5 ldx b x e582 ee ed ldx b y e584 ee f6 ldx d sp e586 ee e6 ldx d x e588 ee ee ldx d y e58a de 55 ldx dir e58c de 55 ldx...

Page 404: ...leas 1 sp e696 1b 1f leas 1 x e698 1b 5f leas 1 y e69a 1b 90 leas 16 sp e69c 1b 10 leas 16 x e69e 1b 50 leas 16 y e6a0 1b f1 ef leas 17 sp e6a3 1b e1 ef leas 17 x e6a6 1b e9 ef leas 17 y e6a9 1b d2 leas small pc e6ab 1b 92 leas small sp e6ad 1b 12 leas small x e6af 1b 52 leas small y e6b1 1b c0 leas 0 pc e6b3 1b 80 leas 0 sp e6b5 1b 00 leas 0 x e6b7 1b 40 leas 0 y e6b9 1b b0 leas 1 sp e6bb 1b 30 l...

Page 405: ...a ea 01 88 leax ext y e7c0 1a f8 37 leax ind pc e7c3 1a f0 37 leax ind sp e7c6 1a e0 37 leax ind x e7c9 1a e8 37 leax ind y e7cc 1a ce leax small pc e7ce 1a 8e leax small sp e7d0 1a 0e leax small x e7d2 1a 4e leax small y e7d4 19 a0 leay 1 sp e7d6 19 20 leay 1 x e7d8 19 60 leay 1 y e7da 19 a7 leay 8 sp e7dc 19 27 leay 8 x e7de 19 67 leay 8 y e7e0 19 c0 leay pc e7e2 19 80 leay sp e7e4 19 00 leay x ...

Page 406: ...8e1 68 e0 7d lsl 125 x e8e4 68 e8 7d lsl 125 y e8e7 68 8f lsl 15 sp e8e9 68 0f lsl 15 x e8eb 68 4f lsl 15 y e8ed 68 f0 10 lsl 16 sp e8f0 68 e0 10 lsl 16 x e8f3 68 e8 10 lsl 16 y e8f6 68 b7 lsl 8 sp e8f8 68 37 lsl 8 x e8fa 68 77 lsl 8 y e8fc 68 b8 lsl 8 sp e8fe 68 38 lsl 8 x e900 68 78 lsl 8 y e902 68 f4 lsl a sp e904 68 e4 lsl a x e906 68 ec lsl a y e908 68 f5 lsl b sp e90a 68 e5 lsl b x e90c 68 e...

Page 407: ... 18 18 28 maxa 8 x ea2a 18 18 68 maxa 8 y ea2d 18 18 9f maxa 1 sp ea30 18 18 1f maxa 1 x ea33 18 18 5f maxa 1 y ea36 18 18 90 maxa 16 sp ea39 18 18 10 maxa 16 x ea3c 18 18 50 maxa 16 y ea3f 18 18 f1 ef maxa 17 sp ea43 18 18 e1 ef maxa 17 x ea47 18 18 e9 ef maxa 17 y ea4b 18 18 d2 maxa small pc ea4e 18 18 92 maxa small sp ea51 18 18 12 maxa small x ea54 18 18 52 maxa small y ea57 18 18 c0 maxa 0 pc...

Page 408: ... maxm b y ebc5 18 1c f6 maxm d sp ebc8 18 1c e6 maxm d x ebcb 18 1c ee maxm d y ebce 18 1c f2 01 88 maxm ext sp ebd3 18 1c e2 01 88 maxm ext x ebd8 18 1c ea 01 88 maxm ext y ebdd 18 1c f8 37 maxm ind pc ebe1 18 1c f0 37 maxm ind sp ebe5 18 1c e0 37 maxm ind x ebe9 18 1c e8 37 maxm ind y ebed 18 1c ce maxm small pc ebf0 18 1c 8e maxm small sp ebf3 18 1c 0e maxm small x ebf6 18 1c 4e maxm small y eb...

Page 409: ... 18 1d bf minm 1 sp ed73 18 1d 3f minm 1 x ed76 18 1d 7f minm 1 y ed79 18 1d f8 7d minm 125 pc ed7d 18 1d f0 7d minm 125 sp ed81 18 1d e0 7d minm 125 x ed85 18 1d e8 7d minm 125 y ed89 18 1d 8f minm 15 sp ed8c 18 1d 0f minm 15 x ed8f 18 1d 4f minm 15 y ed92 18 1d f0 10 minm 16 sp ed96 18 1d e0 10 minm 16 x ed9a 18 1d e8 10 minm 16 y ed9e 18 1d b7 minm 8 sp eda1 18 1d 37 minm 8 x eda4 18 1d 77 minm...

Page 410: ... x ef51 18 0a 22 78 movb 3 x 8 y ef55 18 0a 22 f4 movb 3 x a sp ef59 18 0a 22 e4 movb 3 x a x ef5d 18 0a 22 ec movb 3 x a y ef61 18 0a 22 f5 movb 3 x b sp ef65 18 0a 22 e5 movb 3 x b x ef69 18 0a 22 ed movb 3 x b y ef6d 18 0a 22 f6 movb 3 x d sp ef71 18 0a 22 e6 movb 3 x d x ef75 18 0a 22 ee movb 3 x d y ef79 18 0d 22 01 88 movb 3 x ext ef7e 18 0a 22 ce movb 3 x small pc ef82 18 0a 22 8e movb 3 x ...

Page 411: ...8 0d 30 01 88 movb 1 x ext f17b 18 0a 70 22 movb 1 y 3 x f17f 18 0a 70 6b movb 1 y 5 y f183 18 0a 70 85 movb 1 y 5 sp f187 18 0d 70 01 88 movb 1 y ext f18c 18 0a 81 22 movb 1 sp 3 x f190 18 0a 81 6b movb 1 sp 5 y f194 18 0a 81 85 movb 1 sp 5 sp f198 18 0d 81 01 88 movb 1 sp ext f19d 18 0a 01 22 movb 1 x 3 x f1a1 18 0a 01 6b movb 1 x 5 y f1a5 18 0a 01 85 movb 1 x 5 sp f1a9 18 0d 01 01 88 movb 1 x e...

Page 412: ... 1 sp f39a 18 0a 85 30 movb 5 sp 1 x f39e 18 0a 85 70 movb 5 sp 1 y f3a2 18 0a 85 81 movb 5 sp 1 sp f3a6 18 0a 85 01 movb 5 sp 1 x f3aa 18 0a 85 41 movb 5 sp 1 y f3ae 18 0a 85 bf movb 5 sp 1 sp f3b2 18 0a 85 3f movb 5 sp 1 x f3b6 18 0a 85 7f movb 5 sp 1 y f3ba 18 0a 85 b7 movb 5 sp 8 sp f3be 18 0a 85 37 movb 5 sp 8 x f3c2 18 0a 85 77 movb 5 sp 8 y f3c6 18 0a 85 b8 movb 5 sp 8 sp f3ca 18 0a 85 38 m...

Page 413: ... 78 01 88 movb ext 8 y f5eb 18 09 f4 01 88 movb ext a sp f5f0 18 09 e4 01 88 movb ext a x f5f5 18 09 ec 01 88 movb ext a y f5fa 18 09 f5 01 88 movb ext b sp f5ff 18 09 e5 01 88 movb ext b x f604 18 09 ed 01 88 movb ext b y f609 18 09 f6 01 88 movb ext d sp f60e 18 09 e6 01 88 movb ext d x f613 18 09 ee 01 88 movb ext d y f618 18 0c 01 88 01 88 movb ext ext f61e 18 09 ce 01 88 movb ext small pc f62...

Page 414: ...xt f821 18 02 00 22 movw x 3 x f825 18 02 00 6b movw x 5 y f829 18 02 00 85 movw x 5 sp f82d 18 01 00 00 00 movw x ext f832 18 02 40 22 movw y 3 x f836 18 02 40 6b movw y 5 y f83a 18 02 40 85 movw y 5 sp f83e 18 01 40 00 00 movw y ext f843 18 02 af 22 movw 1 sp 3 x f847 18 02 af 6b movw 1 sp 5 y f84b 18 02 af 85 movw 1 sp 5 sp f84f 18 05 af 01 88 movw 1 sp ext f854 18 02 2f 22 movw 1 x 3 x f858 18...

Page 415: ...w 5 y pc fa4c 18 02 6b 80 movw 5 y sp fa50 18 02 6b 00 movw 5 y x fa54 18 02 6b 40 movw 5 y y fa58 18 02 6b af movw 5 y 1 sp fa5c 18 02 6b 2f movw 5 y 1 x fa60 18 02 6b 6f movw 5 y 1 y fa64 18 02 6b a8 movw 5 y 8 sp fa68 18 02 6b 28 movw 5 y 8 x fa6c 18 02 6b 68 movw 5 y 8 y fa70 18 02 6b 9f movw 5 y 1 sp fa74 18 02 6b 1f movw 5 y 1 x fa78 18 02 6b 5f movw 5 y 1 y fa7c 18 02 6b 90 movw 5 y 16 sp f...

Page 416: ... x 5 y fc62 18 02 37 85 movw 8 x 5 sp fc66 18 05 37 01 88 movw 8 x ext fc6b 18 02 77 22 movw 8 y 3 x fc6f 18 02 77 6b movw 8 y 5 y fc73 18 02 77 85 movw 8 y 5 sp fc77 18 05 77 01 88 movw 8 y ext fc7c 18 02 b8 22 movw 8 sp 3 x fc80 18 02 b8 6b movw 8 sp 5 y fc84 18 02 b8 85 movw 8 sp 5 sp fc88 18 05 b8 01 88 movw 8 sp ext fc8d 18 02 38 22 movw 8 x 3 x fc91 18 02 38 6b movw 8 x 5 y fc95 18 02 38 85 ...

Page 417: ...w small sp 3 x fe85 18 02 8e 6b movw small sp 5 y fe89 18 02 8e 85 movw small sp 5 sp fe8d 18 05 8e 01 88 movw small sp ext fe92 18 02 0e 22 movw small x 3 x fe96 18 02 0e 6b movw small x 5 y fe9a 18 02 0e 85 movw small x 5 sp fe9e 18 05 0e 01 88 movw small x ext fea3 18 02 4e 22 movw small y 3 x fea7 18 02 4e 6b movw small y 5 y feab 18 02 4e 85 movw small y 5 sp feaf 18 05 4e 01 88 movw small y ...

Page 418: ... sp ffda aa 0f oraa 15 x ffdc aa 4f oraa 15 y ffde aa f0 10 oraa 16 sp ffe1 aa e0 10 oraa 16 x ffe4 aa e8 10 oraa 16 y ffe7 aa b7 oraa 8 sp ffe9 aa 37 oraa 8 x ffeb aa 77 oraa 8 y ffed aa b8 oraa 8 sp ffef aa 38 oraa 8 x fff1 aa 78 oraa 8 y fff3 aa f4 oraa a sp fff5 aa e4 oraa a x fff7 aa ec oraa a y fff9 aa f5 oraa b sp fffb aa e5 oraa b x fffd aa ed oraa b y ffff aa f6 oraa d sp 0001 aa e6 oraa ...

Page 419: ...ulx 00f9 31 puly 00fa 18 3a rev 00fc 65 a0 rol 1 sp 00fe 65 20 rol 1 x 0100 65 60 rol 1 y 0102 65 a7 rol 8 sp 0104 65 27 rol 8 x 0106 65 67 rol 8 y 0108 65 c0 rol pc 010a 65 80 rol sp 010c 65 00 rol x 010e 65 40 rol y 0110 65 af rol 1 sp 0112 65 2f rol 1 x 0114 65 6f rol 1 y 0116 65 a8 rol 8 sp 0118 65 28 rol 8 x 011a 65 68 rol 8 y 011c 65 9f rol 1 sp 011e 65 1f rol 1 x 0120 65 5f rol 1 y 0122 65 ...

Page 420: ...021e 66 4f ror 15 y 0220 66 f0 10 ror 16 sp 0223 66 e0 10 ror 16 x 0226 66 e8 10 ror 16 y 0229 66 b7 ror 8 sp 022b 66 37 ror 8 x 022d 66 77 ror 8 y 022f 66 b8 ror 8 sp 0231 66 38 ror 8 x 0233 66 78 ror 8 y 0235 66 f4 ror a sp 0237 66 e4 ror a x 0239 66 ec ror a y 023b 66 f5 ror b sp 023d 66 e5 ror b x 023f 66 ed ror b y 0241 66 f6 ror d sp 0243 66 e6 ror d x 0245 66 ee ror d y 0247 76 00 55 ror di...

Page 421: ... e2 00 sbcb x 034a e2 40 sbcb y 034c e2 af sbcb 1 sp 034e e2 2f sbcb 1 x 0350 e2 6f sbcb 1 y 0352 e2 a8 sbcb 8 sp 0354 e2 28 sbcb 8 x 0356 e2 68 sbcb 8 y 0358 e2 9f sbcb 1 sp 035a e2 1f sbcb 1 x 035c e2 5f sbcb 1 y 035e e2 90 sbcb 16 sp 0360 e2 10 sbcb 16 x 0362 e2 50 sbcb 16 y 0364 e2 f1 ef sbcb 17 sp 0367 e2 e1 ef sbcb 17 x 036a e2 e9 ef sbcb 17 y 036d e2 d2 sbcb small pc 036f e2 92 sbcb small s...

Page 422: ... staa 1 sp 046f 6a 3f staa 1 x 0471 6a 7f staa 1 y 0473 6a f8 7d staa 125 pc 0476 6a f0 7d staa 125 sp 0479 6a e0 7d staa 125 x 047c 6a e8 7d staa 125 y 047f 6a 8f staa 15 sp 0481 6a 0f staa 15 x 0483 6a 4f staa 15 y 0485 6a f0 10 staa 16 sp 0488 6a e0 10 staa 16 x 048b 6a e8 10 staa 16 y 048e 6a b7 staa 8 sp 0490 6a 37 staa 8 x 0492 6a 77 staa 8 y 0494 6a b8 staa 8 sp 0496 6a 38 staa 8 x 0498 6a ...

Page 423: ... y 0596 6c a7 std 8 sp 0598 6c 27 std 8 x 059a 6c 67 std 8 y 059c 6c c0 std pc 059e 6c 80 std sp 05a0 6c 00 std x 05a2 6c 40 std y 05a4 6c af std 1 sp 05a6 6c 2f std 1 x 05a8 6c 6f std 1 y 05aa 6c a8 std 8 sp 05ac 6c 28 std 8 x 05ae 6c 68 std 8 y 05b0 6c 9f std 1 sp 05b2 6c 1f std 1 x 05b4 6c 5f std 1 y 05b6 6c 90 std 16 sp 05b8 6c 10 std 16 x 05ba 6c 50 std 16 y 05bc 6c f1 ef std 17 sp 05bf 6c e1...

Page 424: ...2 6f 77 sts 8 y 06c4 6f b8 sts 8 sp 06c6 6f 38 sts 8 x 06c8 6f 78 sts 8 y 06ca 6f f4 sts a sp 06cc 6f e4 sts a x 06ce 6f ec sts a y 06d0 6f f5 sts b sp 06d2 6f e5 sts b x 06d4 6f ed sts b y 06d6 6f f6 sts d sp 06d8 6f e6 sts d x 06da 6f ee sts d y 06dc 5f 55 sts dir 06de 7f 01 88 sts ext 06e1 6f f2 01 88 sts ext sp 06e5 6f e2 01 88 sts ext x 06e9 6f ea 01 88 sts ext y 06ed 6f f8 37 sts ind pc 06f0...

Page 425: ...ef sty 17 y 07f0 6d d2 sty small pc 07f2 6d 92 sty small sp 07f4 6d 12 sty small x 07f6 6d 52 sty small y 07f8 6d c0 sty 0 pc 07fa 6d 80 sty 0 sp 07fc 6d 00 sty 0 x 07fe 6d 40 sty 0 y 0800 6d b0 sty 1 sp 0802 6d 30 sty 1 x 0804 6d 70 sty 1 y 0806 6d 81 sty 1 sp 0808 6d 01 sty 1 x 080a 6d 41 sty 1 y 080c 6d bf sty 1 sp 080e 6d 3f sty 1 x 0810 6d 7f sty 1 y 0812 6d f8 7d sty 125 pc 0815 6d f0 7d sty...

Page 426: ... ind pc 091b a0 f0 37 suba ind sp 091e a0 e0 37 suba ind x 0921 a0 e8 37 suba ind y 0924 a0 ce suba small pc 0926 a0 8e suba small sp 0928 a0 0e suba small x 092a a0 4e suba small y 092c c0 72 subb immed 092e c0 72 subb immed 0930 e0 a0 subb 1 sp 0932 e0 20 subb 1 x 0934 e0 60 subb 1 y 0936 e0 a7 subb 8 sp 0938 e0 27 subb 8 x 093a e0 67 subb 8 y 093c e0 c0 subb pc 093e e0 80 subb sp 0940 e0 00 sub...

Page 427: ...1 x 0a3f a3 41 subd 1 y 0a41 a3 bf subd 1 sp 0a43 a3 3f subd 1 x 0a45 a3 7f subd 1 y 0a47 a3 f8 7d subd 125 pc 0a4a a3 f0 7d subd 125 sp 0a4d a3 e0 7d subd 125 x 0a50 a3 e8 7d subd 125 y 0a53 a3 8f subd 15 sp 0a55 a3 0f subd 15 x 0a57 a3 4f subd 15 y 0a59 a3 f0 10 subd 16 sp 0a5c a3 e0 10 subd 16 x 0a5f a3 e8 10 subd 16 y 0a62 a3 b7 subd 8 sp 0a64 a3 37 subd 8 x 0a66 a3 77 subd 8 y 0a68 a3 b8 subd...

Page 428: ...l pc 0b59 e7 92 tst small sp 0b5b e7 12 tst small x 0b5d e7 52 tst small y 0b5f e7 c0 tst 0 pc 0b61 e7 80 tst 0 sp 0b63 e7 00 tst 0 x 0b65 e7 40 tst 0 y 0b67 e7 b0 tst 1 sp 0b69 e7 30 tst 1 x 0b6b e7 70 tst 1 y 0b6d e7 81 tst 1 sp 0b6f e7 01 tst 1 x 0b71 e7 41 tst 1 y 0b73 e7 bf tst 1 sp 0b75 e7 3f tst 1 x 0b77 e7 7f tst 1 y 0b79 e7 f8 7d tst 125 pc 0b7c e7 f0 7d tst 125 sp 0b7f e7 e0 7d tst 125 x...

Page 429: ...Memory expansion 10 7 Relative 3 4 ANDA instruction 6 16 ANDB instruction 6 17 ANDCC instruction 6 18 ASL instruction 6 19 ASLA instruction 6 20 ASLB instruction 6 21 ASLD instruction 6 22 ASR instruction 6 23 ASRA instruction 6 24 ASRB instruction 6 25 Asserted 1 3 Automatic indexing 3 8 Automatic program stack 2 2 B Background debugging mode 5 22 8 6 BKGD pin 8 7 to 8 9 Commands 8 9 to 8 10 Enab...

Page 430: ... instruction 6 60 CMPB instruction 6 61 Code size B 10 COM instruction 6 62 COMA instruction 6 63 COMB instruction 6 64 Compare instructions 5 5 6 53 6 60 to 6 61 6 65 to 6 68 Complement instructions 5 6 6 62 to 6 64 Computer operating properly monitor 7 3 Condition codes instructions 5 21 6 18 6 54 to 6 55 6 59 6 153 6 156 6 162 6 182 to 6 184 6 198 6 203 to 6 204 B 15 Condition codes register 2 ...

Page 431: ...ode trap 7 1 to 7 2 7 5 Vectors 7 1 7 6 Exchange instructions 5 2 6 90 6 215 to 6 216 B 11 B 13 Postbyte encoding A 24 Execution cycles 6 5 Conditional 16 bit read 6 7 Conditional 8 bit read 6 7 Conditional 8 bit write 6 7 Free 6 5 Optional 4 4 to 4 5 6 6 Program word access 6 6 Read indirect pointer 6 5 Read indirect PPAGE value 6 5 Read PPAGE 6 5 Read 16 bit data 6 6 Read 8 bit data 6 6 Stack 16...

Page 432: ... 2 5 19 C 2 X 3 5 6 9 6 67 6 70 to 6 71 6 76 6 90 to 6 95 6 100 6 126 6 128 to 6 130 6 158 6 164 6 166 6 168 6 177 6 185 6 191 6 196 6 200 to 6 203 6 209 6 211 6 215 Y 3 5 6 10 6 68 6 70 to 6 71 6 77 to 6 80 6 85 to 6 86 6 90 6 92 to 6 93 6 101 6 127 to 6 130 6 159 6 165 to 6 166 6 168 6 177 6 185 6 192 6 196 6 200 to 6 203 6 210 6 212 6 216 Indexed addressing modes 2 2 3 5 A 22 B 6 to B 9 Accumul...

Page 433: ...nemonics 5 8 LSLA instruction 6 132 LSLB instruction 6 133 LSLD instruction 6 134 LSR instruction 6 135 LSRA instruction 6 136 LSRB instruction 6 137 LSRD instruction 6 138 M Maskable interrupts 7 1 7 4 MAXA instruction 6 139 Maximum instructions 5 11 B 14 16 bit 6 81 to 6 82 8 bit 6 139 to 6 140 MAXM instruction 6 140 9 1 MEM instruction 5 9 6 141 9 1 9 9 to 9 13 Membership functions 9 2 Memory a...

Page 434: ...nter 2 1 to 2 2 3 5 6 31 6 49 6 52 6 103 6 128 to 6 130 6 144 to 6 145 6 150 6 177 to 6 178 6 196 6 201 6 205 Program word access cycle 6 6 Programming model 1 1 2 1 B 3 Pseudo non maskable interrupt 7 2 PSHA instruction 6 154 PSHB instruction 6 155 PSHC instruction 6 156 PSHD instruction 6 157 PSHX instruction 6 158 PSHY instruction 6 159 PULA instruction 6 160 PULB instruction 6 161 PULC instruc...

Page 435: ...n 6 190 STX instruction 6 191 STY instruction 6 192 SUBA instruction 6 193 SUBB instruction 6 194 SUBD instruction 6 195 Subroutine instructions 5 17 Subroutines 4 3 6 103 C 4 to C 5 Expanded memory 4 3 5 17 6 52 6 176 Instructions 5 17 6 49 6 103 C 4 to C 5 Return 6 176 6 178 Subtraction instructions 5 3 6 179 to 6 181 6 193 to 6 195 SWI instruction 5 18 6 196 7 6 Switch statements C 4 Symbols an...

Page 436: ...nstack 8 bit data cycle 6 6 Unweighted rule evaluation 6 166 9 5 9 13 to 9 15 9 17 to 9 20 9 22 9 29 V V status bit 2 4 6 50 to 6 51 6 59 6 120 to 6 121 6 166 to 6 169 6 184 Vector fetch cycle 6 7 Vectors exception 7 1 7 6 W WAI instruction 5 21 6 213 WAV instruction 5 9 5 11 6 214 9 1 9 6 9 22 to 9 24 9 26 9 29 Wavr pseudoinstruction 9 23 to 9 24 9 26 Weighted average 6 214 Weighted rule evaluati...

Page 437: ...ription 6 167 Corrected access detail for REV instruction 6 177 Corrected operation sequence for RTI instruction 6 189 Corrected operation sequence for STOP instruction Also fourth paragraph of description modified so as to not indicate that SP is changed 6 196 Condition code register corrected status bit I is set 1 following the SWI instruction 6 213 Corrected operation sequence for WAI instructi...

Page 438: ...MOTOROLA SUMMARY OF CHANGES CPU12 S 2 REFERENCE MANUAL ...

Page 439: ......

Page 440: ...nal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death ass...

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