xvi
DSP56303 User’s Manual
6-12
Host Port Control Register (HPCR) Bit Definitions................................................ 6-18
6-13
DSP-Side Registers After Reset .............................................................................. 6-22
6-14
Host-Side Register Map........................................................................................... 6-24
6-15
Interface Control Register (ICR) Bit Definitions .................................................... 6-25
6-16
Command Vector Register (CVR) Bit Definitions.................................................. 6-27
6-17
Interface Status Register (ISR) Bit Definitions ....................................................... 6-28
6-18
Host-Side Registers After Reset .............................................................................. 6-31
6-19
HI08 Programming Model, DSP Side ..................................................................... 6-32
6-20
HI08 Programming Model: Host Side ..................................................................... 6-34
7-1
ESSI Clock Sources ................................................................................................... 7-3
7-2
Mode and Signal Definitions ..................................................................................... 7-5
7-3
ESSI Control Register A (CRA) Bit Definitions ..................................................... 7-15
7-4
ESSI Control Register B (CRB) Bit Definitions ..................................................... 7-19
7-5
ESSI Status Register (SSISR) Bit Definitions ......................................................... 7-28
7-6
ESSI Port Signal Configurations ............................................................................. 7-37
8-1
SCI Registers After Reset .......................................................................................... 8-5
8-2
SCI Control Register (SCR) Bit Definitions............................................................ 8-12
8-3
SCI Status Register .................................................................................................. 8-17
8-4
SCI Status Register (SSR) Bit Definitions .............................................................. 8-17
8-5
SCI Clock Control Register (SCCR) Bit Definitions .............................................. 8-19
9-1
Timer Prescaler Load Register (TPLR) Bit Definitions .......................................... 9-27
9-2
Timer Prescaler Count Register (TPCR) Bit Definitions ........................................ 9-28
9-3
Timer Control/Status Register (TCSR) Bit Definitions........................................... 9-28
9-4
Inverter (INV) Bit Operation ................................................................................... 9-32
B-1
Guide to Programming Sheets ...................................................................................B-2
B-2
Internal I/O Memory Map (X Data Memory)...........................................................B-3
B-3
Interrupt Sources........................................................................................................B-8
B-4
Interrupt Source Priorities Within an IPL................................................................B-10
Summary of Contents for DSP56303
Page 1: ...DSP56303 User s Manual 24 Bit Digital Signal Processor DSP56303UM AD Revision 1 January 2001 ...
Page 52: ...JTAG OnCE Interface 2 22 DSP56303 User s Manual ...
Page 114: ...General Purpose Input Output GPIO 5 10 DSP56303 User s Manual ...
Page 212: ...GPIO Signals and Registers 8 26 DSP56303 User s Manual ...
Page 268: ...Interrupt Equates A 22 DSP56303 User s Manual ...
Page 306: ...Programming Sheets B 38 DSP56303 User s Manual ...
Page 320: ...Index 14 DSP56303 User s Manual ...