EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
7 - 26
PROCESSING STATES
MOTOROLA
7.3.7 Interrupt Instruction Execution
Interrupt instruction execution is considered “fast” if neither of the instructions of the
interrupt service routine causes a change of flow. A JSR within a fast interrupt routine
forms a long interrupt, which is terminated with an RTI instruction to restore the PC and
SR from the stack and return to normal program execution. Reset is a special exception,
which will normally contain only a JMP instruction at the exception start address. At the
programmer’s option, almost any instruction can be used in the fast interrupt routine. The
restricted instructions include SWI, STOP, and WAIT. Figure 7-8 and Figure 7-10 show
the fast and the long interrupt service routines. The fast interrupt executes only two
instructions and then automatically resumes execution of the main program; whereas,
the long interrupt must be told to return to the main program by executing an RTI instruc-
tion.
Figure 7-8 illustrates the effect of a fast interrupt routine in the stream of instruction
fetches.
Figure 7-9 shows the sequence of instruction decodes between two fast interrupts. Four
decodes occur between the two interrupt decodes (two after the first interrupt and two
preceding the second interrupt). The requirement for these four decodes establishes the
maximum rate at which the DSP56K will respond to interrupts — namely, one interrupt
every six instructions (six instruction cycles if all six instructions are one instruction cycle
each). Since some instructions take more than one instruction cycle, the minimum num-
ber of instructions between two interrupts may be more than six instruction cycles.
The execution of a fast interrupt routine always conforms to the following rules:
1. A JSR to the starting address of the interrupt service routine is not located at
one of the two interrupt vector addresses.
2. The processor status is not saved.
3. The fast interrupt routine may (but should not) modify the status of the normal
instruction stream.
4. The fast interrupt routine may contain any single two-word instruction or any
two one-word instructions except SWI, STOP, and WAIT.
5. The PC, which contains the address of the next instruction to be executed in
normal processing remains unchanged during a fast interrupt routine.
Summary of Contents for DSP56K
Page 12: ...xii LIST of TABLES MOTOROLA List of Tables Continued Table Page Number Title Number ...
Page 13: ...MOTOROLA DSP56K FAMILY INTRODUCTION 1 1 SECTION 1 DSP56K FAMILY INTRODUCTION ...
Page 31: ...MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 1 SECTION 3 DATA ARITHMETIC LOGIC UNIT ...
Page 50: ...DATA ALU SUMMARY 3 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA ...
Page 51: ...MOTOROLA ADDRESS GENERATION UNIT 4 1 SECTION 4 ADDRESS GENERATION UNIT ...
Page 77: ...MOTOROLA PROGRAM CONTROL UNIT 5 1 SECTION 5 PROGRAM CONTROL UNIT ...
Page 124: ...INSTRUCTION GROUPS 6 30 INSTRUCTION SET INTRODUCTION MOTOROLA ...
Page 125: ...MOTOROLA PROCESSING STATES 7 1 SECTION 7 PROCESSING STATES STOP WAIT EXCEPTION NORMAL RESET ...
Page 167: ...STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 43 ...
Page 168: ...STOP PROCESSING STATE 7 44 PROCESSING STATES MOTOROLA ...
Page 169: ...MOTOROLA PORT A 8 1 SECTION 8 PORT A ...
Page 176: ...PORT A INTERFACE 8 8 PORT A MOTOROLA ...
Page 177: ...MOTOROLA PLL CLOCK OSCILLATOR 9 1 SECTION 9 PLL CLOCK OSCILLATOR x x d Φ VCO ...
Page 191: ...10 2 ON CHIP EMULATION OnCE MOTOROLA SECTION 10 ON CHIP EMULATION OnCE ...
Page 218: ...USING THE OnCE MOTOROLA ON CHIP EMULATION OnCE 10 29 ...
Page 604: ...INSTRUCTION ENCODING A 338 INSTRUCTION SET DETAILS MOTOROLA ...
Page 605: ...MOTOROLA BENCHMARK PROGRAMS B 1 APPENDIX B BENCHMARK PROGRAMS T T T T T P1 P3 P2 P4 T T T ...
Page 609: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 5 ...
Page 611: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 7 ...
Page 613: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 9 ...
Page 615: ...BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B 11 ...