MOTOROLA
53
7.4
Interrupt Priority Register (IPR)
The Interrupt Priority Register supports the timer module with the addition of the Timer0
and Timer1 priority level bits. Figure 21 shows the revised IPR with the new bits indicated
in bold characters.
Figure 21 - Interrupt Priority Register (Address X:$FFFFFFFF)
T1L1
T0L1 T0L0
**
**
**
**
T1L0
Reserved
HBL1 HBL0 HAL1 HAL0 D1L1 D1L0 D0L1 D0L0
IRCS ICL2
ICL1 ICL0
IRBS IBL2 IBL1
IBL0 IRAS IAL2
IAL1 IAL0
DMA Channel 0 IPL
DMA Channel 1 IPL
Host A IPL
Host B IPL
IRQC IPL
IRQC Trigger Mode
IRQC Status
Reserved
IRQA IPL
IRQA Trigger Mode
IRQA Status
IRQB IPL
IRQB Trigger Mode
IRQB Status
**
**
**
**
Timer0 IPL
Timer1 IPL
Summary of Contents for DSP96002
Page 3: ...1 2 DSP96002 USER S MANUAL MOTOROLA ...
Page 38: ...MOTOROLA DSP96002 USER S MANUAL 3 15 Figure 3 4 Modulo Arithmetic Unit Block Diagram ...
Page 39: ...3 16 DSP96002 USER S MANUAL MOTOROLA ...
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Page 76: ...MOTOROLA DSP96002 USER S MANUAL 5 23 Figure 5 8 Address Modifier Summary ...
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Page 101: ...MOTOROLA DSP96002 USER S MANUAL 7 15 Figure 7 9 HI Block Diagram One Port ...
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Page 181: ...MOTOROLA DSP96002 USER S MANUAL 10 15 Figure 10 8 Program Address Bus FIFO ...
Page 337: ...MOTOROLA DSP96002 USER S MANUAL A 149 ...
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Page 460: ...A 272 DSP96002 USER S MANUAL MOTOROLA SIOP Not affected ...
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Page 519: ...MOTOROLA DSP96002 USER S MANUAL A 331 ...
Page 718: ...MOTOROLA DSP96002 USER S MANUAL B 199 ...
Page 871: ... MOTOROLA INC 1994 MOTOROLA TECHNICAL DATA SEMICONDUCTOR M Addendum ...
Page 888: ...MOTOROLA INDEX 1 INDEX ...
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