M68360QUADS-040 Hardware User’s Manual
FUNCTIONAL DESCRIPTION
31
WARNNING
Additional BSRAM components should be soldered with care.
Otherwise permanent damage may be inflicted to the
M68360QUADS-040.
The bursting sram may be accessed by both the EC040 and the DMA, however access by the QUICC must
be EVEN WORD aligned.
4.9
EEPROM
The EEPROM used in the M68360QUADS-040 is Motorola MCM2814, 256 byte serial EEPROM (U14).
The slave QUICC provides 4 signals to control accesses to the EEPROM.
The MCM2814 has internal hardware protection against inadvertent writes to the EEPROM that might
happen at power up or power down time.
4.10
DRAM
The M68360QUADS-040 is supplied with 1 Mbyte of Dynamic RAM, which is implemented by the
MCM36256S-60 DRAM module. The module is a 72 lead SIMM, 60 nsec access time, organized as 256K
x 36 bit for data and parity signals, and is accessed with 3,2,2,2 clock cycles during burst cycles and 3
clocks during normal read / write access.
It is possible to replace the supplied DRAM SIMM with a higher density module in order to increase the
DRAM memory space up to 8 Mbyte. The higher density modules may require using RAS1 and RAS2
signals of the slave QUICC if they are organized as two memory banks. After hard / power-up reset, the
status register is read to detect the kind of dram SIMM inserted, in order to initialize the CS registers with
the correct data regarding the dram’s size and delay.
The DRAM is controlled by the slave QUICC device, using its DRAM controller function for normal
accesses, burst mode accesses, and refresh accesses. The DRAM can be accessed by the master
68EC040 and the slave QUICC’s DMA channels.
NOTE:
Due to problems of implementation, the QUICC’s support for
68EC040’s burst mode inhibits the support for internal page
mode. Therefore, the I/SDMAs access the DRAM using
normal access pattern only.
4.11
Slave QUICC
During normal operation, the CPU of the slave QUICC is disabled, and the device is used to implement the
following functions on the ADS:
1.
DRAM Controller
2.
Chip Select TA~ and DSACK~ generator.
3.
Parallel port (ADI) controller.
4.
UART for terminal or host computer connection.
5.
Ethernet controller.
The address of the MBAR register is configured to $0033FF00.
The QUICC’s peripherals (such as the IDMA and SDMA) can request the bus and become bus master,
even though the CPU is disabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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