Motorola M68MPBF333, User Manual

Page 1: ...M68MPB333UM D REV 1 March 1998 M68MPBF333 MCU PERSONALITY BOARD USER S MANUAL MOTOROLA INC 1994 1998 All Rights Reserved ...

Page 2: ... the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of direct...

Page 3: ... W3 2 7 2 2 4 Voltage Reference Low Select Header W4 2 8 2 2 5 VSSA Insertion Point E1 2 8 2 3 MEVB CONFIGURATION 2 10 2 4 ACTIVE PROBE CONFIGURATION 2 12 CHAPTER 3 MEVB QUICK START GUIDE 3 1 INTRODUCTION 3 1 3 2 CONFIGURING THE MPFB 3 1 3 2 1 MPFB Memory Devices 3 1 3 2 2 MPFB Jumper Headers 3 2 3 3 MEVB INSTALLATION INSTRUCTIONS 3 3 3 3 1 Power Supply MPFB Connection 3 3 3 3 2 Personal Computer ...

Page 4: ...5 4 MAPI Interface Connector P3 Pin Assignments 5 4 5 5 MAPI Interface Connector P4 Pin Assignments 5 5 TABLES 1 1 MPB Specifications 1 2 2 1 Jumper Header Types 2 4 2 2 MPB Jumper Header Descriptions 2 4 3 1 MPFB Quick Start Jumper Header Configuration 3 2 4 1 Logic Analyzer Connector J7 Pin Assignments 4 2 4 2 Logic Analyzer Connector J8 Pin Assignments 4 2 4 3 Logic Analyzer Connector J9 Pin As...

Page 5: ...ES continued 4 11 Logic Analyzer Connector J17 Pin Assignments 4 9 4 12 Logic Analyzer Connector J18 Pin Assignments 4 10 4 13 Logic Analyzer Connector J19 Pin Assignments 4 11 4 14 Logic Analyzer Connector J20 Pin Assignments 4 11 ...

Page 6: ...CONTENTS vi M68MPB333UM D ...

Page 7: ...he MEVB consists of the M68MPFB Modular Platform Board MPFB and an MPB Alternately you may install the MPB directly in your target system if the target system includes a modular active probe interconnect MAPI interface The MCU device on the MPB defines which MCU is emulated evaluated by the MMDS or evaluated by the MEVB Both systems are invaluable tools for designing debugging and evaluating MCU o...

Page 8: ...tible Temperature Operating Storage 0 to 40 C 40 to 85 C Relative humidity 0 to 90 non condensing Power requirements 5Vdc 5 500 mA max Dimensions MCU Personality Board 3 25 x 3 25 in 82 6 x 82 6 mm 1 3 EQUIPMENT REQUIRED The external requirements for MPB operation are either an MPFB or MMDS system For MMDS operation requirements see the MMDS1632 Motorola Modular Development System User s Manual MM...

Page 9: ...852 6106888 Tai Po 852 6668333 INDIA Bangalore 91 80 5598615 ISRAEL Herzlia 972 9 590222 ITALY Milan 39 2 82201 JAPAN Fukuoka 81 92 725 7583 Gotanda 81 3 5487 8311 Nagoya 81 52 232 3500 Osaka 81 6 305 1802 Sendai 81 22 268 4333 Takamatsu 81 878 37 9972 Tokyo 81 3 3440 3311 KOREA Pusan 82 51 4635 035 Seoul 82 2 554 5118 MALAYSIA Penang 60 4 2282514 MEXICO Mexico City 52 5 282 0230 Guadalajara 52 36...

Page 10: ...GENERAL INFORMATION 1 4 M68MPB333UM D ...

Page 11: ...mper installed on a jumper header provides a connection between two points in the MPB circuit The MPB has two types of jumper headers three pin and two pin with a cut trace short A cut trace short has a copper trace between the feed through holes bottom or solder side of the MPB Table 2 1 describes each type of jumper header The MPB has four jumper headers for which Table 2 2 is a quick reference ...

Page 12: ...e multi layer circuit board If the cut trace short on a jumper header is already cut you can return the MPB to its default setting by installing a user supplied fabricated jumper MCU Clock Source Reference Mark VDDA Source VRH Source External Ground Connection VRL Source MPB333B 01 RE90379W C1 REV 1993 R1 C2 R2 C3 W1 L2 L1 Y1 U1 MC68F333 RN2 L3 RN1 RN3 C10 RN4 S N C4 C5 C6 C7 C8 C9 C12 C13 C14 C15...

Page 13: ... Y1 C3 R1 W1 W4 W3 RN2 C4 C5 L3 C6 RN3 RN1 L1 RN4 1993 01 RE90427W MPB33C REV R2 R3 R4 C7 C8 C9 C10 C11 L2 MCU Clock Source W2 E1 Reference Mark VDDA Source VRH Source External Ground Connection VRL Source Figure 2 2 M68MPBF333 C version Parts Location Diagram top view ...

Page 14: ...Jumper between pins 1 and 2 factory default selects the MPB on board crystal clock source Jumper between pins 2 and 3 selects an external clock sourceto be the MCU EXTAL input signal W2 1 2 Jumper installed or cut trace short intact factory default selects the on board VDDA power source No jumper or cut trace short lets you connect an external power source to W2 pin 2 and the external power source...

Page 15: ...CU allows via the internal phase locked loop or direct clock input If you install the MPB in the active probe or directly on a target system and use the target system clock as the MPB clock move the fabricated jumper to W1 pins 2 and 3 This connects the MCU EXTAL pin to the MAPI bus input pin The frequency of the external clock signal can be from 32 KHz to 16 78 MHz or to the maximum the MCU allow...

Page 16: ...ternal power source to W2 pin 2 Removal of the cut trace short isolates the MCU VDDA pin from the other MPB circuitry Isolation lets you connect a precision VDDA source for accurate 10 bit analog digital A D generation When connecting an external VDDA power supply to the MPB connect the power supply ground to insertion point E1 For more information on A D generation refer to the Analog To Digital ...

Page 17: ...fabricated jumper on W3 pins 2 and 3 Then connect the MCU VRH pin to the external VRH source Each configuration defines the best method for connecting the MCU VRH pin to the external VRH source MPB MPFB connect via the MPFB logic analyzer connector refer to Chapter 4 for the appropriate logic analyzer pin MPB MMDS1632 connect via the VRH pin of the target MCU socket MPB Target System connect via t...

Page 18: ...ng the MCU VRL pin to the external VRL source MPB MPFB connect via the MPFB logic analyzer connector refer to Chapter 4 for the appropriate logic analyzer pin MPB MMDS1632 connect via the VRL pin of the target MCU socket MPB Target System connect via the VRL pin of the target system MAPI bus Alternately you may remove the jumper and wire wrap directly to W4 pin 2 Connecting directly to pin 2 is an...

Page 19: ... help you get started using your MEVB CAUTION Turn OFF MPFB power when installing the MPB on the MPFB or removing the MPB from the MPFB Sudden power surges could damage MEVB integrated circuits To install the MPB on the MPFB refer to Figure 2 3 1 Inspect all connectors for bent or damaged pins 2 Align the MPB reference mark with the MPFB reference mark 3 Rotate the MPB until the four MAPI bus conn...

Page 20: ...connection with SDI Interface After you have installed the MPB install the plastic overlay on the MPFB place the overlay over logic analyzer connectors J12 through J20 and press down Holes in the overlay slide down over plastic clips on the MPFB These clips hold the overlay in place ...

Page 21: ...active probe and the station module 01 RE90340W01 REV 0 and 01 RE90341W01 REV 0 are printed on the active probe cables The active probe cables come with the MMDS For more information about the active probe cables refer to the M68MMDS1632 Motorola Modular Development System User s Manual MMDS1632UM D Active probe box the protective enclosure for the TCB CAUTION Turn off MMDS and target system power...

Page 22: ...end of the 01 RE90340W01 REV 0 active probe cable to connector P5 on the MMDS control board connect the other end to connector J5 on the TCB Secure the connector clamps on TCB connectors J5 and J6 The active probe is now ready to connect to the target system refer to the PPB configuration guide for information on connecting the active probe to the target system Figure 2 4 Active Probe Interconnect...

Page 23: ...e MPB 3 2 CONFIGURING THE MPFB This paragraph explains the MPFB jumper headers for operation with the M68MPBF333 The MPFB includes jumper selectable options such as chip select usage memory type selection and memory size selection for the pseudo ROM sockets and reset data control NOTE The MPFB must be configured for the specific MPB Paragraph 3 2 2 provides a configuration for rudimentary MPFB ope...

Page 24: ...sable the PRU W10 1 3 5 2 4 6 Install a jumper on pins 1 and 2 to indicate that RAM is installed in the pseudo ROM sockets U2 U4 W12 1 3 5 7 9 2 4 6 8 10 Install a jumper on pins 3 and 4 to indicate that the two devices installed in the pseudo ROM sockets U2 U4 are 32K x 8 W14 1 2 3 Jumper header W14 selects the MCU signal for the memory devices in the fast RAM sockets U9 U10 and pseudo ROM socket...

Page 25: ...and host computer The host computer must have a parallel port and must run MS DOS as required by ICD32 The following paragraphs explain MPFB connections Refer to Chapter 2 for instructions to connect the MPB and MPFB 3 3 1 Power Supply MPFB Connection Use MPFB connector J5 Figure 3 1 to connect a user supplied power supply to the MEVB Contact 1 is ground black lever Contact 2 is VDD 5 volts red le...

Page 26: ...igure 3 1 MPFB Power Supply Connector CAUTIONS Do not use wire larger than 20 AWG in connector J5 Such wire could damage the connector Turn off MEVB power when installing or removing the MPB from the MPFB Sudden power surges could damage MEVB integrated circuits ...

Page 27: ... 4 SOFTWARE INSTALLATION AND MCU INITIALIZATION After you have set up the MEVB hardware you must installthe software on your computer Follow the installation procedure in the appropriate software operations manual The MCU must be initialized before the MEVB will function The following is one possible initialization for the MPB333 You may adapt this example to your debugger This initialization enab...

Page 28: ...CSBOOT block size to 64K mm w CSORBT 7830 Change wait state to zero mdf6 START Display program in PMM window D0 00000000 D1 00000000 D2 00000000 D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 000101FE symbol SRAMBAH FFFB44 symbol SRAMMCR FFFB40 mmw SRAMBAH 0001 Set SRAM Base Address mmb SRAMMCR 00 T...

Page 29: ... variables in F6 area var w CSBARBT var w SCIMCR Show variables in F6 area var w SYNCR asciiF3 Show F3 area as ASCII characters bf 400 2000 0 Using Block Fill to pause macro execution mdf6 Now show memory values in F6 area asciiF3 Now show memory values in F3 area PC START Enter your program here ...

Page 30: ...MEVB QUICK START GUIDE 3 8 M68MPB333UM D ...

Page 31: ... MPB type 4 2 LOGIC ANALYZER CONNECTOR SIGNALS The tables of this chapter describe MPFB logic analyzer connector signalsif you install an M68MPBF333 on the MPFB The signal descriptions on J12 J20 are the logic analyzer pin outs on the plastic overlay supplied with the MPB NOTE The signal descriptions in the following tables are for quick reference only The MC68F333 User s Manual MC68F333UM AD cont...

Page 32: ...omplement negated contents of the PEPAR register 12 19 PE7 PE0 PORT E I O SIGNALS PRU replacement of the port E function 20 GND GROUND Table 4 2 Logic Analyzer Connector J8 Pin Assignments Pin Mnemonic Signal 1 2 SPARE No connection 3 OE ABG I O PRU OUTPUT ENABLE Input active high when low disables port A port B and port G outputs 4 11 PA7 PA0 PORT A I O SIGNALS PRU replacement of the port A funct...

Page 33: ... G I O SIGNALS PRU replacement of the port G function 20 GND GROUND Table 4 4 Logic Analyzer Connector J10 Pin Assignments Pin Mnemonic Signal 1 5V 5 VDC POWER Input voltage 5Vdc 1 0 A used by the MEVB logic circuits To make this pin a no connection remove the jumper from jumper header W9 on the MPFB 2 SPARE No connection 3 AS ADDRESS STROBE Active low output signal that indicates whether a valid ...

Page 34: ...Logic Analyzer Connector J12 Pin Assignments Pin Mnemonic Signal 1 2 SPARE No connection 3 CLKOUT SYSTEM CLOCK OUT Output signal that is the MCU internal system clock 4 BERR BUS ERROR Active low signal that indicates a memory access error has occurred 5 BKPT DSCLK BREAKPOINT Active low input signal that signals a hardware breakpoint to the CPU Development Serial Clock Clock input signal for backgr...

Page 35: ...sizing between the MCU and external devices 12 DSACK0 DATA AND SIZE ACKNOWLEDGE 0 Active low input signal that allows asynchronous data transfers and dynamic bus sizing between the MCU and external devices 13 FC2 CS5 FUNCTION CODE 2 Output signal that identifies the processor state and address space of the current bus cycle CHIP SELECT 5 Output signal that selects peripheral or memory devices at p...

Page 36: ...rts 20 GND GROUND Table 4 7 Logic Analyzer Connector J13 Pin Assignments Pin Mnemonic Signal 1 5V 5 VDC POWER Input voltage 5Vdc 1 0 A used by the MEVB logic circuits To make this pin a no connection remove the jumper from jumper header W21 on the MPFB 2 SPARE No connection 3 DSACK1 DATA AND SIZE ACKNOWLEDGE 1 Active low input signal that allows asynchronous data transfers and dynamic bus sizing b...

Page 37: ...HIP SELECT CSM is not supported on the MC68F333 MCU 10 CSBOOT BOOT CHIP SELECT An active low output chip select for external boot startup ROM 11 CLKOUT SYSTEM CLOCK OUTPUT MCU internal clock output signal 12 A23 CS10 ADDRESS BUS BIT 23 One bit of the 24 bit address bus CHIP SELECT 10 Output signal that selects peripheral or memory devices at programmed addresses 13 A22 CS9 ADDRESS BUS BIT 22 One b...

Page 38: ...data transfers and dynamic bus sizing between the MCU and external devices 4 MODCLK CLOCK MODE SELECT Input signal that configures the MCU internal clock at reset 5 TSC THREE STATE CONTROL When TSC is logic high this input signal forces all output drivers to a high impedance state 6 RESET RESET Active low bi directional signal to start a system reset 7 RMC READ MODIFY WRITE CYCLE Active low output...

Page 39: ...zer Connector J16 Pin Assignments Pin Mnemonic Signal 1 4 SPARE No connection 5 12 TPU0 TPU7 TIME PROCESSOR UNIT CHANNELS TPU input output channels 13 19 SPARE No connection 20 GND GROUND Table 4 11 Logic Analyzer Connector J17 Pin Assignments Pin Mnemonic Signal 1 4 SPARE No connection 5 6 GND GROUND 7 RXD RECEIVE DATA Serial data input line to serial communication interface 8 TXD TRANSMIT DATA S...

Page 40: ...nal from the SPI in slave mode the clock signal to the SPI 14 MOSI MASTER OUT SLAVE IN Serial output from SPI in master mode serial input to SPI in slave mode 15 MISO MASTER IN SLAVE OUT Serial input to SPI in master mode serial output from SPI in slave mode 16 GND GROUND 17 19 SPARE No connection 20 GND GROUND Table 4 12 Logic Analyzer Connector J18 Pin Assignments Pin Mnemonic Signal 1 4 SPARE N...

Page 41: ...ice 16 VSSA A D GROUND A D ground reference 17 19 SPARE No connection 20 VSSA A D GROUND A D ground reference Table 4 13 Logic Analyzer Connector J19 Pin Assignments Pin Mnemonic Signal 1 4 SPARE No connection 5 12 PADB0 PADB7 ADC DIGITAL OUTPUT PORT BITS 0 7 Analog output bits from the MCU ADC port 13 19 SPARE No connection 20 GND GROUND Table 4 14 Logic Analyzer Connector J20 Pin Assignments Pin...

Page 42: ...MEVB SUPPORT INFORMATION 4 12 M68MPB333UM D ...

Page 43: ...ter show the MAPI interface connector layout and pin assignments for MPB connectors P1 P2 P3 and P4 Figures 5 1 through 5 5 5 2 MAPI BUS CONNECTORS The connectors required to interface to the MAPI bus are 2 Robinson Nugent 2 X30 plugs P50L 060P AS TGF 2 Robinson Nugent 2 X40 plugs P50L 080P AS TGF 2 500 1 250 2 500 1 250 C L 1 1 1 1 C L C L C L C L C L Figure 5 1 MAPI Interface Connector Layout ...

Page 44: ...TPUCH11 33 n n 34 GND TPUCH12 35 n n 36 GND TPUCH13 37 n n 38 GND TPUCH14 39 n n 40 GND TPUCH15 41 n n 42 GND T2CLK 43 n n 44 GND GND 45 n n 46 GND GND 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 GND A23 CS10 E 55 n n 56 GND A22 CS9 PC6 57 n n 58 GND A21 CS8 PC5 59 n n 60 GND A20 CS7 PC4 61 n n 62 GND A19 CS6 PC3 63 n n 64 GND FC2 CS5 PC2 65 n n 66 GND FC1 PC1 67 n n 68 GND FC0...

Page 45: ...1 A5 PB2 25 n n 26 A6 PB3 A7 PB4 27 n n 28 A8 PB5 A9 PB6 29 n n 30 GND A10 PB7 31 n n 32 A11 PA0 A12 PA1 33 n n 34 A13 PA2 A14 PA3 35 n n 36 A15 PA4 A16 PA5 37 n n 38 A17 PA6 A18 PA7 39 n n 40 GND VFPE48K 41 n n 42 5V GND 43 n n 44 GND VSSA 45 n n 46 VSSA VSSA 47 n n 48 PADA0 AN0 VSSA 49 n n 50 PADA1 AN1 VSSA 51 n n 52 PADA2 AN2 VSSA 53 n n 54 PADA3 AN3 VSSA 55 n n 56 MAPI VRL VSSA 57 n n 58 MAPI ...

Page 46: ...D GND 31 n n 32 GND GND 33 n n 34 GND GND 35 n n 36 GND GND 37 n n 38 GND GND 39 n n 40 GND GND 41 n n 42 GND GND 43 n n 44 GND GND 45 n n 46 GND GND 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 VSTBY GND 55 n n 56 DSO IPIPE GND 57 n n 58 DSI IFETCH GND 59 n n 60 HALT GND 61 n n 62 RESET GND 63 n n 64 BERR GND 65 n n 66 BKPT DSCLK GND 67 n n 68 TSC GND 69 n n 70 FREEZE GND 71 n ...

Page 47: ...D A0 23 n n 24 GND DSACK0 PE0 25 n n 26 GND DSACK1 PE1 27 n n 28 GND AVEC PE2 29 n n 30 GND RMC PE3 31 n n 32 GND DS PE4 33 n n 34 GND AS PE5 35 n n 36 GND SIZ0 PE6 37 n n 38 GND SIZ1 PE7 39 n n 40 GND R W 41 n n 42 GND MODCLK PF0 43 n n 44 GND IRQ1 PF1 45 n n 46 GND IRQ2 PF2 47 n n 48 GND IRQ3 PF3 49 n n 50 GND IRQ4 PF4 51 n n 52 GND IRQ5 PF5 53 n n 54 GND IRQ6 PF6 55 n n 56 GND IRQ7 PF7 57 n n 5...

Page 48: ...MAPI SUPPORT INFORMATION 5 6 M68MPB16Y3UM D ...

Page 49: ...6 1 CHAPTER 6 SCHEMATIC DIAGRAMS 6 1 INTRODUCTION This chapter contains the M68MPB916R3 MCU Personality Board MPB schematic diagrams These schematic diagrams are for reference only and may deviate slightly from the circuits on your MPB ...

Page 50: ...ADER DATE DATE TITLE MPBF333B SCHEMATIC R G 10 26 93 TITLE REVISITION STATUS 1 TABLE OF CONTENTS 2 NOTES 6 MCU CLOCK 4 MODULAR ACTIVE PROBE INTERCONNECT P1 P3 3 BYPASS CAPACITORS CLEAN POWER SIGNAL FILTERS 5 MODULAR ACTIVE PROBE INTERCONNECT P2 P4 7 PULLUPS PULLDOWNS PERSONALITY ID A REV DWG NO SIZE GEDABV SHEET DWG NO REV GEDTTL A D 3 1 2 C B 4 A D C 3 1 2 4 MPBF333B 1 OF 8 A 63ASE90379W LAST_MOD...

Page 51: ...LL 16 PIN ICS PIN 20 OF ALL 20 PIN ICS ETC ALL VOLTAGES ARE DC ALL CAPACITORS ARE IN UF ALL RESISTORS ARE IN OHMS 5 1 8 WATT IS AS FOLLOWS 1 UNLESS OTHERWISE SPECIFIED 2 INTERRUPTED LINES CODED WITH THE 3 DEVICE TYPE NUMBER IS FOR REFERENCE 4 SPECIAL SYMBOL USAGE 5 INTERPRET DIAGRAM IN ACCORDANCE 6 CODE FOR SHEET TO SHEET REFERENCES INPUT OUTPUT REVISION WITH THE EXCEPTION OF INSTITUTE SPECIFICATI...

Page 52: ...8 A REV DWG NO SIZE GEDABV SHEET DWG NO REV GEDTTL A D 3 1 2 C B 4 A D C 3 1 2 4 MPBF333B 3 OF 8 A 63ASE90379W LAST_MODIFIED Wed Jun 22 15 37 05 1994 BOARD 63ASE90379W A 0 1UF C8 BYPASS CAPACITORS CLEAN POWER SIGNAL FILTERS CUT TRACE ON BOARD ANALOG SIGNAL FILTERS ADC MODULE VDDA VSSA GENERATION ADC MODULE VDDI VSSI GENERATION 5V AND GND DECOUPLING FOR VDDE OF MCU AND OSCILLATOR VRH VRL SELECTION ...

Page 53: ... I O VSTBY DSO DSI HALT RESET BERR BKPT TSC FREEZE GND GND CLKOUT GND VDD RN P50L 080S BS TGF P3 MAPI BUS P1 MAPI BUS P3 MODULAR ACTIVE PROBE INTERCONNECT P1 P3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 79 78...

Page 54: ...2 A A N 3 L O G A RN P50L 060S BS TGF P2 MODULAR ACTIVE PROBE INTERCONNECT P2 P4 MAPI BUS P2 MAPI BUS P4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 55: ...5V VDDI GND VSSI VSSI VSSI VSSI VDDI W1 VDDA NOTE 1 PLACE THE CAP BETWEEN VDDSYN XFC AS CLOSE TO MCU PINS AS POSSIBLE 2 THE CAP BETWEEN XFC VSSI IS OPTIONAL MCU CLOCK 14 PIN DIP SOCKET FOR 8 OR 14 PIN CANS DIPS 11 8 2 1 2 1 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 ...

Page 56: ... 12 13 7 10 6 9 5 4 16 3 14 15 2 1 3 4 5 6 13 12 11 10 9 7 16 8 12 11 10 9 8 7 6 5 1 2 3 15 14 13 16 4 RXD TXD PCS3 PCS2 PCS1 PCS0 SS SCK MOSI MISO IRQ 7 1 PADB 7 0 PADB 5 PADB 6 PADB 7 PADB 4 PADB 3 PADB 2 PADB 0 PADB 1 IRQ 3 IRQ 4 IRQ 5 IRQ 6 IRQ 7 IRQ 1 IRQ 2 1M NC NC NC NC T2CLK TPU 15 0 TPU 0 TPU 2 TPU 1 TPU 3 TPU 5 TPU 4 TPU 6 TPU 7 TPU 9 TPU 8 TPU 11 TPU 12 TPU 10 TPU 15 TPU 13 TPU 14 1M 1M...

Page 57: ...B4 R W 5C4 6C4 PCS3 5C1 6B4 7B4 HALT 4B1 6C4 RESET 4B1 6C4 RMC 5C4 6D4 RXD 5C1 6A4 7B4 SCK 4C4 6B4 7B4 SIZ0 5C4 6D4 SIZ1 5C4 6C4 T2CLK 4B4 6B4 7C4 TPU 15 0 4C4 6C4 7C4 TSC 4B1 6D1 TXD 5C1 6B4 7B4 VFPE16K 4A4 6B1 VFPE48K 5B1 6B1 VRH 3B4 6B1 VRL 3B4 6B1 VSTBY 4B1 6C1 FREEZE 4A1 6D1 Signal Cross Reference for the entire design A 18 0 5D4 6D1 7D1 AN 7 0 3B1 4C1 5B1 6C1 AS 5C4 6D4 AVEC 5C4 6D4 BERR 4B1...

Page 58: ...SCHEMATIC DIAGRAMS 6 10 M68MPB333UM D ...