ENV - Set Environment
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PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in the IBC
(PCI/ISA bus bridge controller). The ENV parameter is a 32-bit value
that is divided by 4 to yield the values for route control registers
PIRQ0/1/2/3. The default is determined by system type. For details on
PCI/ISA interrupt assignments and for suggested values to enter for
this parameter, refer to the 8259 Interrupts section in Chapter 4 of the
MCP750 Programmer’s Reference Guide, listed in
Serial Startup Code Master Enable [Y/N]=N?
The Serial Startup Codes can be displayed at key points in the
initialization of the hardware devices. Should the debugger fail to
come up to a prompt, the last code displayed will indicate how far the
initialization sequence had progressed before stalling. The codes are
enabled by an ENV parameter.
Serial Startup Code LF Enable [Y/N]=N?
A line feed can be inserted after each code is displayed to prevent it
from being overwritten by the next code. This is also enabled by an
ENV parameter.
A list of LED/serial codes is included in the section on MPU,
Hardware, and Firmware Initialization in Chapter 1 of the PPCBug
Firmware Package User’s Manual, Part 1.
Claim domain A [Y/N] = N?
This parameter controls whether or not the processor attempts to claim
domain A during initial startup or after a reset has been issued. An
attempt to power on all non-host processor boards found in domain A
will be made. In a dual host processor system, if domain A is owned
by the other host processor, no attempt will be made to claim the
domain or power on slots. (Default = N)
A
L2 Cache parity is always enabled.
N
L2 Cache parity is never enabled
Summary of Contents for MCP750HA Series
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