2-4
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Operating Instructions
2
Notes
1. Default map for PCI/ISA I/O space. Allows software to
determine whether the system is MPC105-based or
Falcon/Raven-based by examining either the PHB Device ID or
the CPU Type register.
2. The first 1MB of ROM/Flash bank A (soldered 4MB or 8MB
ROM/Flash) appears in this range after a reset if the rom_b_rv
control bit in the Falcon’s ROM B Base/Size register is cleared.
If the rom_b_rv control bit is set, this address range maps to
ROM/Flash bank B (socketed 1MB ROM/Flash).
For detailed processor memory maps, including suggested PREP-
compatible memory maps, refer to the MCP750 Single Board Computer
Programmer's Reference Guide (MCP750A/PG), listed in
PCI Local Bus Memory Map
The PCI memory map is controlled by the Raven ASIC and by the 21154
PCI-to-PCI bridges. The Raven and the PCI-to-PCI bridges adjust system
mapping to suit a given application via programmable map decoder
registers.
No default PCI memory map exists. Resetting the system turns the PCI
map decoders off, and they must be reprogrammed in software for the
intended application.
FEF90000
FEFEFFFF
384KB
Not Mapped
FEFF0000
FEFFFFFF
64KB
Raven Registers
FF000000
FFEFFFFF
15MB
Not Mapped
FFF00000
FFFFFFFF
1MB
ROM/Flash Bank A or Bank B
2
Table 2-1. Processor Default View of the Memory Map (Continued)
Processor Address
Size
Definition
Notes
Start
End
Summary of Contents for MCP750HA Series
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