Memory Maps
http://www.motorola.com/computer/literature
2-5
2
For detailed PCI memory maps, including suggested PREP-compatible
memory maps, refer to the MCP750 Single Board Computer
Programmer's Reference Guide, listed in
CompactPCI Memory Map
The processor will access devices on the CompactPCI busses by using
transaction forwarding provided by the DEC 21154 PCI-to-PCI bridge.
Transaction forwarding within the 21154 is based on address ranges
defined in the 21154 base and limit registers. The 21154 provides registers
for I/O, memory, and prefetchable memory spaces. These registers define
the address range for which PCI transactions are forwarded downstream
from the primary PCI bus to the CompactPCI bus (secondary bus). All
devices on the CompactPCI bus must be configured for addressing within
this defined range. Conversely, these registers also define the addresses for
which transactions will be forwarded upstream. Any CompactPCI bus
address, generated by a CompactPCI bus master, not in the defined
memory range, will be forwarded upstream, to the Primary PCI bus. There
is no address translation between CompactPCI busses and the Primary PCI
bus.
Recommendations for CompactPCI mapping, including suggested PREP-
compatible memory maps, can be found in the MCP750 Single Board
Computer Programmer's Reference Guide.
PCI Arbitration
There are 6 potential local PCI bus masters on the MCP750HA single-
board computer:
❏
Raven ASIC (MPU/PCI bus bridge controller)
❏
DEC 21154 PCI-to-PCI bridge
❏
External PCI bus master via J4 connector, used by the hot swap
bridge
❏
VIA 82C586B PBC (Peripheral Bus Controller) PCI/ISA bridge
Summary of Contents for MCP750HA Series
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