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Functional Description
3
❏
Counter 0 is associated with interrupt request line IRQ0. It can be
used for system timing functions, such as a timer interrupt for a
time-of-day function.
❏
Counter 1 generates a refresh request signal for ISA memory. This
timer is not used in the MCP750HA.
❏
Counter 2 provides the tone for the speaker output function on the
PBC (the
SPEAKER_OUT
signal which can be cabled to an external
speaker via the transition module).
The interval timers use the OSC clock input as their clock source. The
MCP750HA drives the OSC pin with a 14.31818 MHz clock source.
16-Bit Timers
Three 16-bit timers, provided by the Z8536 CIO device, are available on
the MCP750HA. For information on programming these timers, refer to
the data sheet for the Z8536 CIO device.
Serial Communications Interface
The MCP750HA uses a Zilog Z85230 Enhanced Serial Communications
Controller (ESCC) to implement the two serial communications interfaces,
which are routed through the transition module. The Z85230 supports
synchronous (SDLC/HDLC) and asynchronous protocols. The
MCP750HA hardware supports asynchronous serial baud rates of 110B/s
to 38.4 KB/s.
Each interface supports the CTS, DCD, RTS, and DTR control signals as
well as the TxD and RxD transmit/receive data signals, and TxC/RxC
synchronous clock signals. Since not all modem control lines are available
in the Z85230, a Z8536 CIO is used to provide the missing modem lines.
A PAL device performs decoding of register accesses and pseudo interrupt
acknowledge cycles for the Z85230 and the Z8536 in ISA I/O space. The
PBC controller supplies DMA support for the Z85230.
The Z85230 receives a 10 MHz clock input. The two synchronous ports
will support data transfers up to 2.5 Mbits/sec. The Z85230 supplies an
interrupt vector during pseudo interrupt acknowledge cycles. The vector is
Summary of Contents for MCP750HA Series
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