CONTENTS
Paragraph
Number
Title
Page
Number
Contents
xv
DMA Mode Registers (DMRs)..................................................................... 8-15
Current Descriptor Address Registers (CDARs) .......................................... 8-19
Destination Address Registers (DARs) ........................................................ 8-21
DAR and BCR Values—Double PCI Write ................................................. 8-22
Next Descriptor Address Registers (NDARs) .............................................. 8-23
2
O)
Message and Doorbell Register Programming Model........................................ 9-2
Message and Doorbell Register Summary...................................................... 9-2
9.3
O Interface ....................................................................................................... 9-5
9.3.2
O Register Summary.................................................................................... 9-5
Inbound Free_List FIFO ......................................................................... 9-8
Inbound Post_List FIFO ......................................................................... 9-8
Outbound Free_List FIFO ...................................................................... 9-8
Outbound Post_List FIFO ...................................................................... 9-9
9.3.4
O Register Descriptions ............................................................................... 9-9
9.3.4.1
O Registers..................................................................... 9-9
Outbound Message Interrupt Status Register (OMISR)......................... 9-9
Outbound Message Interrupt Mask Register (OMIMR) ...................... 9-10
Inbound FIFO Queue Port Register (IFQPR)....................................... 9-11
Outbound FIFO Queue Port Register (OFQPR)................................... 9-12
9.3.4.2
2
O Registers ......................................................... 9-12
Inbound Message Interrupt Status Register (IMISR) ........................... 9-12
Inbound Message Interrupt Mask Register (IMIMR)........................... 9-14
Inbound Free_FIFO Head Pointer Register (IFHPR)........................... 9-15
Inbound Free_FIFO Tail Pointer Register (IFTPR) ............................. 9-16
Inbound Post_FIFO Head Pointer Register (IPHPR) ........................... 9-16
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...