14-12
MPC8240 Integrated Processor User’s Manual
Example Code Sequence for Entering Processor and Peripheral Logic Sleep Modes
execute in program order despite the address munging that causes little endian addressing
of instructions already in the cache. If the processor is operating in big-endian mode, these
no-op instructions are not needed.
*********************************************************************
# First set up peripheral logic power management register
# and the processor core HID0 power management bits
#*********************************************************************
#*********************************************************************
# turn on power management bits
#
addis r3, r0, 0x8000 # start building new register number
ori r3, r3, 0x0070 # register number 0xf0
stwbrx r3, r0, r1 # write this value to CONFIG_ADDR
sync
lhbrx r4, r0, r2 # load r4 from CONFIG_DATA
addis r0, r0, 0x0000 # PM=1
ori r0, r0, 0xc088 # set bits 15, 14, and 7, 3(sleep)
or r4, r4, r0 # set the PM bit
sync
sthbrx r4, r0, r2 #
write
the
modified
data
to
CONFIG_DATA
sync
#******processor HID and external interrupt initialization*******************
#
# set up HID registers for the various PowerPC processors
# hid setup taken from minix's mpxPowerPC.s
mfspr r31, pvr # pvr reg
srawi r31, r31, 16
resetTest603:
cmpi 0, 0, r31, 3
bne cr0, endHIDSetup
addi r0, r0, 0
oris r0, r0, 0x1000 # enable machine check pin EMCP
oris r0, r0, 0x0010 # enable dynamic power mgmt DPM
oris r0, r0, 0x0020 # enable SLEEP power mode
ori r0, r0, 0x8000 # enable the Icache ICE
ori r0, r0, 0x4000 # enable the Dcache DCE
ori r0, r0, 0x0800 # invalidate Icache ICFI
ori r0, r0, 0x0400 # invalidate Dcache DCFI
mtspr hid0, r0
isync
#******************************************************************
# then when the processor is in a loop, force an SMI interrupt
#******************************************************************
.orig 0x00001400 # System management interrupt
# force big endian mode
stw r0,0x05f8,r0 # need nop every second inst to make
#code read and execute in program order (up until the isync).
stw r0,0x05fc,r0
mfmsr r0
ori r0,r0,r0
ori r0,r0,0x0001 # force big endian LE bit
ori r0,r0,r0
xori r0,r0,0x0001 # force big endian LE bit
ori r0,r0,r0
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...