CONTENTS
Paragraph
Number
Title
Page
Number
Contents
ix
Processor Compatibility Hole and Alias Space .............................................. 3-7
PCI Compatibility Hole and Alias Space ....................................................... 3-9
Outbound PCI Address Translation .............................................................. 3-13
Local Memory Base Address Register (LMBAR) ................................... 3-15
Inbound Translation Window Register (ITWR)....................................... 3-15
Outbound Memory Base Address Register (OMBAR) ............................ 3-16
Outbound Translation Window Register (OTWR)................................... 3-17
Embedded Utilities Memory Block (EUMB) ................................................... 3-18
Processor Core Control and Status Registers ............................................... 3-18
Peripheral Control and Status Registers ....................................................... 3-19
Configuration Register Access in Little-Endian Mode................................... 4-2
Configuration Register Access in Big-Endian Mode ..................................... 4-3
Processor-Accessible Configuration Registers........................................... 4-5
PCI-Accessible Configuration Registers .................................................... 4-8
PCI Command Register—Offset 0x04 ......................................................... 4-11
Programming Interface—Offset 0x09 .......................................................... 4-14
PCI Base Class Code—Offset 0x0B............................................................. 4-14
PCI Cache Line Size—Offset 0x0C ............................................................. 4-14
PCI Base Address Registers—LMBAR and PCSRBAR ............................. 4-15
PCI Arbiter Control Register (PACR)—Offset 0x46 ................................... 4-16
Peripheral Logic Power Management Configuration Registers (PMCRs) ....... 4-17
Power Management Configuration Register 1 (PMCR1)—Offset 0x70...... 4-17
Power Management Configuration Register 2 (PMCR2)—Offset 0x72...... 4-18
Output/Clock Driver and Miscellaneous I/O Control Registers ....................... 4-20
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...