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MPC8240 Integrated Processor User’s Manual
Detailed Signal Descriptions
Timing Comments
Assertion—NMI may occur at any time, asynchronously.
Negation—Should not occur until after the interrupt is taken.
(interrupt source assumed to be cleared by software in the interrupt
handler routine).
2.2.5.5 System Management Interrupt (SMI)—Input
Following are the state meaning and timing comments for SMI.
State Meaning
Asserted—The SMI input signal is level-sensitive, and causes
exception processing for a system management interrupt when SMI
is asserted and MSR[EE] is set.
Negated—Indicates that normal operation should proceed.
Timing Comments
Assertion—May occur at any time and may be asserted
asynchronously to the input clocks.
Negation—Should not occur until the interrupt is taken.
2.2.5.6 Checkstop In (CHKSTOP_IN)—Input
Following are the state meaning and timing comments for the CHKSTOP_IN signal.
State Meaning
Asserted—Indicates that the MPC8240 processor core must
terminate operation by internally gating off all clocks, and releasing
all processor-related outputs to the high-impedance state.
Negated—Indicates that normal operation should proceed.
Timing Comments
Assertion—May occur at any time and may be asserted
asynchronously to the input clocks.
Negation—Must remain asserted until the system has been reset with
a hard reset.
2.2.5.7 Time Base Enable (TBEN)—Input
Following are the state meaning and timing comments for TBEN.
State Meaning
Asserted—Indicates that the time base and decrementer should
continue clocking. This input is essentially a count enable control for
the time base counter and the decrementer.
Negated—Indicates that the time base and decrementer should stop
clocking.
Timing Comments
Assertion/Negation—May occur on any cycle.
2.2.5.8 Quiesce Acknowledge (QACK)—Output
The quiesce acknowledge (QACK) signal is an output on the MPC8240.It is also a reset
configuration input signal. See Chapter 14, “Power Management,” for more information
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...