Chapter 6. MPC8240 Memory Interface
6-15
SDRAM Interface Operation
Figure 6-5. SDRAM Registered Memory Interface
The in-line buffer mode interface is shown in Figure 6-6. In-line buffer mode allows for
ECC or parity generation and checking between the internal processor core bus and the
external SDRAM data bus. In-line ECC is described in Section 6.2.10, “SDRAM In-Line
ECC.”
Figure 6-6.
. SDRAM In-line ECC/Parity Memory Interface
D
Q
SDRAM data path
Internal Data to SDRAM
External Data from SDRAM
Output Enable
Internal Bus Clock
Q
D
Data Signals
ECC or Parity
check/correct
Parity
Generate
SDRAM data path
D
Q
Q
D
D
Q
Q
D
ECC or Parity
Generate
Parity Check
collect
error
signals
Error signals to Peripheral Logic
Data Signals
Output enable
Internal Data to SDRAM
Internal Bus Clock
External Data from SDRAM
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...