Chapter 7. PCI Bus Interface
7-29
Exclusive Access
initiator of the special-cycle transaction can insert wait states but since there is no specific
target, the special-cycle message and optional data field are valid on the first clock IRDY is
asserted. All special-cycle transactions are terminated by master-abort; however, the
master-abort bit in the initiator’s status register is not set for special-cycle terminations.
7.5 Exclusive Access
PCI provides an exclusive access mechanism referred to as a resource lock. The mechanism
locks only the selected PCI resource (typically memory) but allows other nonexclusive
accesses to unlocked targets. In this section, the term ‘locked operation’ means an exclusive
access to a locked target that may span several PCI transactions. A full description of
exclusive access is contained in the PCI Local Bus Specification, rev 2.1.
The LOCK signal indicates that an exclusive access is underway. The assertion of GNT
does not guarantee control of the LOCK signal. Control of LOCK is obtained in
conjunction with GNT. When using the resource lock, agents performing nonexclusive
accesses are free to proceed even while another master retains ownership of LOCK.
7.5.1 Starting an Exclusive Access
To initiate a locked operation, an initiator must receive GNT when the LOCK signal is not
busy. The initiator is then said to own the LOCK signal. To request a resource lock, the
initiator must hold LOCK negated during the address phase of a read command and assert
LOCK in the clock cycle following the address phase. Note that the first transaction of a
locked operation must be a read transaction.
The locked operation is not established on the PCI bus until the first data transfer (IRDY
and TRDY asserted) completes. Once the lock is established, the initiator may retain
ownership of the LOCK signal and the target may remain locked beyond the end of the
current transaction. The initiator holds LOCK asserted until either the locked operation
completes or until an error (master-abort or target-abort) causes an early termination. A
target remains in the locked state until both FRAME and LOCK are negated. If the target
retries the first transaction without a data phase completing, the initiator should not only
terminate the transaction but also negate LOCK.
7.5.2 Continuing an Exclusive Access
When the lock owner is granted access to the bus for another exclusive access to the
previously-locked target, it negates the LOCK signal during the address phase to reestablish
the lock. The locked target accepts the transaction and claims the transaction. The initiator
then asserts LOCK in the clock cycle following the address phase. If the initiator plans to
continue the locked operation, it continues to assert LOCK.
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...