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MPC8240 Integrated Processor User’s Manual
DMA Register Descriptions
Figure 8-9 shows the bits in the BCRs.
Figure 8-9. Byte Count Register (BCR)
Table 8-8 describes the bit settings for the BCRs.
8.7.7 DAR and BCR Values—Double PCI Write
Note that when the DMA controller is programmed for local memory to PCI or PCI-to-PCI
memory transfers, certain values programmed in the DAR and BCR can cause the DMA
controller to write the last beat of data twice. Although no data corruption occurs and the
status register updates normally after the second beat of the double write has completed,
care must be taken if the device on the PCI bus is a FIFO-like structure.
The combination of DAR and BCR values that result in the double write can be determined
as follows:
(DAR + BCR) mod 0x20 = R,
where R= 0x09–0x0C, 0x11–0x14, or 0x19–0x1C
Example 1: DMA 42 (decimal) bytes from 0x0000_0000 to 0x8000_0000
R = (DAR + BCR) mod 0x20
R = (0x800 0x2A) mod 0x20
R = (2,147,483,648d + 42d) mod 32d
R = 10d = 0x0A
R = 0x0A which is in the range of 0x09–0x0C; therefore, double write of last beat to PCI
will occur.
Example 2: DMA 50 (decimal) bytes from 0x0009_0000 to 0x0009_4FE0.
R = (DAR + BCR) mod 0x20
R = (0x000 0x32) mod 0x20
R = (610,272d + 50d) mod 32d
R = 18d = 0x12
R = 0x12 which is in the range of 0x11–0x14; therefore, double write of last beat to PCI
will occur.
Table 8-8. BCR Field Descriptions—Offsets 0x120, 0x220
Bits
Name
Reset
Value
R/W
Description
31–26
—
All 0s
RW
Reserved
25–0
BCR
All 0s
RW
Byte count. Contains the number of bytes to transfer. The value in this register is
automatically decremented by the MPC8240 after each DMA read operation until
BCR = 0.
0 0 0 0 0 0
BCR
31
26 25
0
Reserved
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...