15-16
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
8
GR2
Grant support of SCC2
0 SCC2 transmitter does not support the grant mechanism. The grant is always asserted
internally.
1 SCC2 transmitter supports the grant mechanism as determined by the GMx bit of a serial
device channel.
9
SC2
SCC2 connection
0 SCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC2 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
10Ð12 RS2CS
Receive SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).
000 SCC2 receive clock is BRG1.
001 SCC2 receive clock is BRG2.
010 SCC2 receive clock is BRG3.
011 SCC2 receive clock is BRG4.
100 SCC2 receive clock is CLK11.
101 SCC2 receive clock is CLK12.
110 SCC2 receive clock is CLK3.
111 SCC2 receive clock is CLK4.
13Ð15 TS2CS
Transmit SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).
000 SCC2 transmit clock is BRG1.
001 SCC2 transmit clock is BRG2.
010 SCC2 transmit clock is BRG3.
011 SCC2 transmit clock is BRG4.
100 SCC2 transmit clock is CLK11.
101 SCC2 transmit clock is CLK12.
110 SCC2 transmit clock is CLK3.
111 SCC2 transmit clock is CLK4.
16
GR3
Grant support of SCC3
0 SCC3 transmitter does not support the grant mechanism. The grant is always asserted
internally.
1 SCC3 transmitter supports the grant mechanism as determined by the GMx bit of a serial
device channel.
17
SC3
SCC3 connection
0 SCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC3 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
18Ð20 RS3CS
Receive SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).
000 SCC3 receive clock is BRG1.
001 SCC3 receive clock is BRG2.
010 SCC3 receive clock is BRG3.
011 SCC3 receive clock is BRG4.
100 SCC3 receive clock is CLK5.
101 SCC3 receive clock is CLK6.
110 SCC3 receive clock is CLK7.
111 SCC3 receive clock is CLK8.
Table 15-6. CMXSCR Field Descriptions (Continued)
Bits
Name
Description
Summary of Contents for MPC8260 PowerQUICC II
Page 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
Page 66: ...lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA ...
Page 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 120: ...2 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
Page 184: ...4 46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II ConÞguration and Reset ...
Page 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 266: ...8 34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 382: ...10 106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 392: ...11 10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 430: ...Part IV viii MOTOROLA Part IV Communications Processor Module ...
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Page 980: ...A 4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Appendixes ...
Page 1002: ...Index 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA INDEX ...
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