MOTOROLA
Chapter 26. Serial Management Controllers (SMCs)
26-31
Part IV. Communications Processor Module
26.5.2 Handling the GCI Monitor Channel
The following sections describe how the GCI monitor channel is handled.
26.5.2.1 SMC GCI Monitor Channel Transmission Process
Monitor channel 0 is used to exchange data with a layer 1 device (reading and writing
internal registers and transferring of the S and Q bits). Monitor channel 1 is used for
programming and controlling voice/data modules such as CODECs. The core writes the
byte into the TxBD. The SMC sends the data on the monitor channel and handles the A and
E control bits according to the GCI monitor channel protocol. The
TIMEOUT
command
resolves deadlocks when errors in the A and E bit states occur on the data line.
26.5.2.2 SMC GCI Monitor Channel Reception Process
The SMC receives data and handles the A and E control bits according to the GCI monitor
channel protocol. When the CP stores a received data byte in the SMC RxBD, a maskable
interrupt is generated. A
TRANSMIT
ABORT
REQUEST
command causes the MPC8260 to
send an abort request on the E bit.
26.5.3 Handling the GCI C/I Channel
The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends
commands and receives indication to or from the upstream layer 1 device through C/I
channel 0. In the SCIT conÞguration, C/I channel 1 is used to convey real-time status
information between the layer 2 device and nonlayer 1 peripheral devices (CODECs).
26.5.3.1 SMC GCI C/I Channel Transmission Process
The core writes the data byte into the C/I TxBD and the SMC transmits the data
continuously on the C/I channel to the physical layer device.
26.5.3.2 SMC GCI C/I Channel Reception Process
The SMC receiver continuously monitors the C/I channel. When it recognizes a change in
the data and this value is received in two successive frames, it is interpreted as valid data.
This is called the double last-look method. The CP stores the received data byte in the C/I
RxBD and a maskable interrupt is generated. If the SMC is conÞgured to support SCIT
channel 1, the double last-look method is not used.
Summary of Contents for MPC8260 PowerQUICC II
Page 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
Page 66: ...lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA ...
Page 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 120: ...2 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
Page 184: ...4 46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II ConÞguration and Reset ...
Page 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 266: ...8 34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 382: ...10 106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 392: ...11 10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 430: ...Part IV viii MOTOROLA Part IV Communications Processor Module ...
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Page 980: ...A 4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Appendixes ...
Page 1002: ...Index 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA INDEX ...
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