29-83
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
29.12.1.1 UTOPIA Master Multiple PHY Operation
The cell transfer in a multiple PHY ATM port uses cell-level handshaking as deÞned in the
UTOPIA standards. The MPC8260 supports two polling modes:
¥
Direct polling uses CLAV[0Ð3] with PHY selection using ADD[0Ð2]. Up to four
PHYs can be supported.
¥
Multiplex polling uses CLAV[0] and ADD[0Ð4]. ATM controller polls all active
PHYs starting from PHY address 0x0 to the address written in
FPSMR[LAST_PHY]. Up to 31 PHY devices are supported.
Both modes support round-robin priority or Þxed priority, described in Section 29.13.2,
ÒFCC Protocol-SpeciÞc Mode Register (FPSMR).Ó
29.12.2 UTOPIA Interface Slave Mode
UTOPIA slave signals are shown in Figure 29-58
Figure 29-58. UTOPIA Slave Mode Signals
RxDATA[0Ð15]
/[0Ð7]
Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using
UTOPIA 16/8, RxDATA[0] is the lsb.
RxSOC
Receive start of cell. Asserted by the PHY device as the Þrst byte of a cell is received on RxDATA.
RxENB
Receive enable. An ATM controller asserts to indicate that RxDATA and RxSOC will be sampled at
the end of the next RxCLK cycle. For multiple PHYs, RxENB is used to three-state RxDATA and
RxSOC at each PHYÕs output. RxDATA and RxSOC should be enabled only in cycles after those with
RxENB asserted.
RxCLAV[0Ð3]
Receive cell available. Asserted by a PHY device when it has a complete cell to give the ATM
controller.
RxPRTY
Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA. If there is a
RxPRTY error and the receive parity check FPSMR[RxP] is enabled, the cell is discarded. See
Section 29.13.2, ÒFCC Protocol-SpeciÞc Mode Register (FPSMR).Ó
RxCLK
Receiver clock. Synchronization reference for RxDATA, RxSOC, RxENB, RxCLAV, and RxPRTY, all of
which are sampled at low-to-high transitions of RxCLK.
RxADD[0Ð4]
Receive address. Address bus from the ATM controller to the PHY device used to select the
appropriate M-PHY device. Each M-PHY device needs to maintain its address. RxADD[4] is the msb.
Table 29-44. UTOPIA Master Mode Signal Descriptions (Continued)
Signal Description
TXDATA[0Ð15]/[0Ð7]
TXSOC
TXENB
TXPRTY
TXCLK
TXCLAV
TXADD[0Ð4]
MPC8260
RXDATA[0Ð15]/[0Ð7]
RXSOC
RXENB
RXPRTY
RXCLK
RXCLAV
RXADD[0Ð4]
MPC8260
Summary of Contents for MPC8260 PowerQUICC II
Page 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
Page 66: ...lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA ...
Page 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 120: ...2 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
Page 184: ...4 46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II ConÞguration and Reset ...
Page 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
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