MOTOROLA
Chapter 30. Fast Ethernet Controller
30-21
Part IV. Communications Processor Module
30.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)
The FCCE, shown in Figure 30-6, is used as the Ethernet event register when the FCC
functions as an Ethernet controller. It generates interrupts and reports events recognized by
the Ethernet channel. On recognition of an event, the Ethernet controller sets the
corresponding FCCE bit. Interrupts generated by this register can be masked in the Ethernet
mask register (FCCM).
The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a
bit masks the corresponding interrupt in the FCCE.
The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not
5
FDE
Full duplex Ethernet
0 Disable full-duplex.
1 Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed.
6
MON
RMON mode
0 Disable RMON mode.
1 Enable RMON mode.
7Ð8
Ñ
Reserved, should be cleared.
9
PRO
Promiscuous
0 Check the destination address of incoming frames.
1 Receive the frame regardless of its address. A CAM can be used for address Þltering when
FSMR[CAM] is set.
10
FCE
Flow control enable
0 Flow control is not enabled.
1 Flow control is enabled.
11
RSH
Receive short frames
0 Discard short frames (frames smaller than the value speciÞed in MINFLR).
1 Receive short frames.
12Ð20
Ñ
Reserved, should be cleared.
21
CAM
CAM address matching
0 Normal operation.
1 Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame.
22
BRO
Broadcast address
0 Receive all frames containing the broadcast address.
1 Reject all frames containing the broadcast address unless FSMR[PRO] = 1.
23
Ñ
Reserved, should be cleared.
24Ð25
CRC
CRC selection
0x Reserved.
10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +
X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet speciÞcations.
11 Reserved.
26Ð31
Ñ
Reserved, should be cleared.
Table 30-8. FPSMR Ethernet Field Descriptions (Continued)
Bits
Name
Description
Summary of Contents for MPC8260 PowerQUICC II
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