Motorola MVME135, User Manual

Page 1: ...MVMEI35 D2 MVME135 MVME135 1 MVME135A MVME136 y AND MVMEl36A 32 Bit Microcomputers User s Manual Y r f t Il I fi0 MOTOROLA j tf t f II rc r A v t_ y 0 4 ...

Page 2: ...tions of these bits will be accurate The second case involves bit three of the ISR the Counter Timer Ready bit This bit may be set after a power up or reset condition and prior to being read by software In the lSR The reason for this is that the HC68681 powers up in the free running timer mode and the timer may reach the end of a count down sequence setting the Counter Tim r Ready bit at any time ...

Page 3: ...65 PHOENIX ARIZONA POSTAGE WILL BE PAID BY ADDRESSEE ee G 2t ut DW164 2900 South Diablo Way Tempe AZ 85282 9741 1 1 I 1 1 I II I 1 1 1 1 1 1 1 II I II 0 5 3 0 5 0 0 0 c a z c 3 c c 0 2 8 0 l NO POSTAGE NECESSARY IF MAILED IN THE UNITED STATES m Z i C l ...

Page 4: ...x etc Is the information easy to understand 0 Yes 0 No If you checked no please explain Is the information easy to find 0 Yes 0 No If you checked no please explain Technical Accuracy 0 Excellent 0 Very Good 0 Good 0 Fair 0 Poor If you have found technical or typographical errors please list them here PaRe Number DescriPtion of Error ...

Page 5: ...t not remove equipment covers Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power...

Page 6: ...Microcomputers This manual is intended for anyone who wants to design OEM systems supply additional capabil ity to an existing compatible system or in a 1ab environment for experimental purposes A bas i c knowl edge of computers and di gita1 1ogi cis assumed To use this manual you should be faimilar with the publications listed in the Re7ated Documentation paragraph in Chapter 1 of this manual ...

Page 7: ...AL MAY CAUSE INTERFERENCE TO RADIO COMMUNICATIONS IT HAS BEEN TESTED AND FOUND TO COMPLY WITH THE LIMITS FOR A CLASS A COMPUTING DEVICE PURSUANT TO SUBPART J OF PART 15 OF FCC RULES WHICH ARE DESIGNED TO PROVIDE REASONABLE PROTECTION AGAINST SUCH INTERFERENCE WHEN OPERATED IN A COMMERCIAL ENVIRONMENT OPERATION OF THIS EQUIPMENT IN A RESIDENTIAL AREA IS LIKELY TO CAUSE INTERFERENCE IN WHICH CASE TH...

Page 8: ...MYMEI35 MYMEI35 1 MVMEI35A MVME136 AND MVMEl36A 32 BIT MICROCOMPUTERS USER S MANUAL MVMEI35jD2 ...

Page 9: ... inaccuracies Furthermore Motorola reserves the right to make changes to any products herei n to improve rel i abi 1i ty function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights or the rights of others ...

Page 10: ...Factory Test Jumper J5 2 6 2 3 4 RAM Acknowledge Mode J6 2 6 2 3 5 ROM Size Select J7 2 7 2 3 6 DRAM Address Multiplex Select J8 2 8 2 3 7 Local VMEbus Timeout Disable Jll 2 8 2 3 8 DRAM Cycle Start Mode Select J12 2 9 2 3 9 External Timer Select JI3 J14 2 10 2 4 SERIAL PORT CABLING 2 11 2 4 1 DB 9 To DB 25 Cable Connection 2 11 2 5 VME CHASSIS INSTALLATION 2 12 CHAPTER 3 OPERATING INSTRUCTIONS 3 ...

Page 11: ...4 9 4 10 2 MC68851 Breakpoint Operation 4 10 4 10 3 MC68851 Breakpoint Architecture 4 11 4 10 4 MC68851 Acknowledge Cycle Operation 4 12 4 10 5 Access Level Control 4 12 4 10 6 Coprocessor Communications 4 13 4 11 INTERRUPT HANDLER 4 14 4 12 ONBOARD ROM PROM EPROM 4 17 4 13 DUAL SERIAL PORTS 4 17 4 14 MVME135 136 TIMER 4 17 4 15 LOCAL CONTROL STATUS REGISTERS 4 18 4 15 1 Status Register Format And...

Page 12: ...RATIONS Jumper Connector And Switch Location Diagram MVME135 136 Front Panel MVME135 135 1 136 Slave Access Addressing MVMEI35A 136A Slave Access Addressing MVME135 135 1 136 Block Diagram MVME135A 136A Block Diagram CPU Space Type Field Encoding Breakpoint Acknowledge Cycle Address Encoding Breakpoi nt Regi sters Breakpoint Acknowledge Data Register Format Breakpoint Acknowledge Control Register ...

Page 13: ...35 1 136 Main Memory Map MVt E135A 136A Main Memory Map MVMEl35 136 Timing Function Code Assignments ALC Interface Registers Map MC68851 Coprocessor Interface Register Map MC68881 Coprocessor Interface Register Map Interrupt Handler Priority Assignments Multiprocessor Control Status Registers Mapping On The VMEbus Connector PI Interconnect Signals Connector P2 Interconnect Signal s Connector J3 In...

Page 14: ...ersions only 4Mb of shared local DRAM with one wait cycle 32 bit wide accessible from the VMEbus with optional parity MVME135A version only 4Mb of shared local DRAM with two wait cycles 32 bit wide accessible from the VMEbus with optional parity MVME136A version only Parity does not add any additional wait cycles for this version On board socket for MC68881 Floating Point Coprocessor FPCP at 16 67...

Page 15: ... provided in the following table Sections 1 2 2 and 1 2 3 detail cooling requ i rements and FCC compl i ance respect i vely TABLE 1 1 MVME135 136 SPECIFICATIONS Characteristic Specification Microprocessor MC68 120 32 bit microprocessor Clock signal MVME135 135A 136 136A 16 67 MHz CPU clock frequency MVME135 1 20 0 1 MHz CPU clock frequency Power requirements MVMEI35 135 1 135A MVME136 136A 1 2 5 V...

Page 16: ...t panel A Z8036A programmable timer module with three independent 16 bit timers Any seven possible VMEbus interrupts can be recei ved by the MVMEl35 136 VSBbus has interrupt capability as do most on board devices 1Mb 0 wa it state wi thout parity and 1 wait state wi th pari ty 1Mb 1 wait state without parity and 2 wait states with parity The MC68851 Paged Memory Management Unit PMMU adds 1 wait st...

Page 17: ...rd cage where the incoming airstream first encounters the board under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors speci fi cat ions are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperatur...

Page 18: ...nit PMMU a Floating Point Coprocessor FPCP and interfaces to the VMEbus and the VSBbus The MVME135 136 is designed for those applications which require fast on board RAM and a secondary bus VSBbus The features of the MVME135 136 include high performance and an elegant architecture The MVME135 136 is especially suited to applications requiring multiple processors where the efficiency of inter proce...

Page 19: ...Memory Management Unit U M MC68881 Floating Point Coprocessor U M MVME204 1 2 Dual Ported Dynamic Memory U M MVME204 2F Dual Ported Dynamic Memory U M MVME224 1 2 4 8Mb Dynami c Memory U M MVSB2400 VSBchip U M VME System Architecture Guide VME Subsystem Bus VSBbus Specification RevA 1 135bug Diagnostic Debug Package U M MOTOROLA PUBLICATION NUMBER MC68020UM AD MC68851UrVAD MC68881UM AD MVME204 MVM...

Page 20: ...ersand specifies a hexadecimal number specifies a binary number specifies a decimal number Unless otherwise specified all address references are in hexadecimal throughout this manual An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significan...

Page 21: ...a GENERAL INFORMATION 1 8 ...

Page 22: ...CUITS STATIC DISCHARGE CAN DAMAGE THESE CIRCUITS Inspect for any shipping damage If no damage exists then the module can be prepared for operation according to the following sect ions of thi s chapter 2 3 HARDWARE PREPARATION This section describes the hardware preparation for the MVME135 136 prior to installation Observance of this description will ensure the user that all components are properly...

Page 23: ...LE SHOWN REMOVED FOR CLARITY J5 DS2 DS3 I I LED INDICATORS EVEN U56 o MC68851 EXTENDED VMEbus I VSBbus P2 VSB DEVICE U75 1 OR BY PASS BOARD MC6B020 ____ AI ODD J11 J8 1 I I SERIAL PORT 2 SERIAL PORT 1 FIGURE 2 1 JUMPER CONNECTOR AND SWITCH LOCATION DIAGRAM r 0 o IE 0 0 0 0 0 I o z ...

Page 24: ...ndi cators The following table lists and describes the MVME135 136 jumper blocks TABLE 2 1 JUMPER BLOCK PLACEMENTS Jumper Function Factory Confi guration J1 VMEbus Lock for VSBbus No jumper installed Disabled J2 Bus Grant Reques t Level Select J2 l 2 5 6 7 8 9 11 10 12 16 18 J3 Mezzan i ne Memory Connect 27 pin connector J4 Mezzan i ne Memory Connect 56 pin connector J5 Factory Test Jumper No jump...

Page 25: ...r jumper option to allow their use with the lock feature described above This jumper does not need to be installed if the system software executes only TAS Test And Set RMC instruction cycles Jumper Block JI VMEbus Lock Disabled No Jumper Installed Factory Setting Fl 2 3 2 Bus Grant Request Level Select J2 Jumper Block JI VMEbus Lock Enabled Jumper Installed The VMEbus has four prioritized bus req...

Page 26: ...7 1 1 8 9 0 0 10 9 0 0 10 11 1 I 12 11 1 I 12 13 I 0 14 13 0 I 14 15 0 16 15 0 16 17 0 0 18 17 0 0 18 Jumper Block J2 Jumper Block J2 Bus Grant Request Level 3 Bus Grant Request Level 2 Factory Setting 1 I 2 1 1 1 2 3 0 0 4 3 0 0 4 5 1 I 6 5 1 I 6 7 I I 8 7 1 I 8 9 10 9 I I 10 11 1 I 12 11 12 13 0 0 14 13 0 0 14 15 I 0 16 15 0 I 16 17 0 18 17 0 18 2 5 ...

Page 27: ...re that a jumper cap is installed at jumper J6 pins 1 and 2 when parity is not required The other case where a jumper cap must be installed at pins 2 and 3 is to accommodate slower DRAM devices Note that the MVME135A and MVME136A versions utilize slower 1M bit DRAMs therefore jumper J6 is confi gured for 1 wait state operat i on For no wa it state operation at 16 67 MHz a 70 nanosecond memory mezz...

Page 28: ... x 8 27256 or 64K x 8 27512 size EPROMs ROMs These two device sizes are the only ones supported These ROM sockets are usually occupied by 135bug a powerful debug package resident in two 275 2 EPROM devices optional therefore a jumper cap is normally installed at jumper J7 pins 2 and 3 The MVME135 135A 136 136A versions 16 67 MHz require that the EPROM ROM device access times be no greater than 300...

Page 29: ...er cap across jumper Jll pins 1 and 2 will prevent the cycle from being terminated by a bus error when a slave does not respond This allows ease in debug since the hung access will remain as long as the cyc1 e is not termi nated by a normal acknowl edge When 135bug is installed the MVME135 136 will not come up if a jumper cap is installed at Jll pins 1 and 2 This is due to the fact that as a cours...

Page 30: ...the CPU clock This is the case when operating with a MC68020 alone or with the combination of a MC68020 and a MC68851 PMMU The asynchronous mode allows for t imi ng strobes that do not have any relationship to the MC68020 clock The case where this jumper is installed would be when a Memory Management Board is used M68KVMMB851 NOTE Use of the Memory Management Board is not planned for the MVME135 1...

Page 31: ...he watch dog timer function Location monitor 2 is also accessible as an input clock source to the Z8036 Thi s coul d be set up to count events or perform synchronizing functions Some of the jumper pins are not intended to be jumper configured These provide external access to timer 2 s trigger and timer 3 s output trigger and gate signals These signals can be connected to other circuitry via wire w...

Page 32: ...ce 135Bug expects the terminal to be attached to serial port one Serial port 2 may be used as another terminal interface or as a connection to a host system for upload download using S Record format Connect on To A Term na1 OB 9 08 25 Connector Connector 2 to 2 3 to 3 8 to 4 7 to 5 4 to 8 5 to 7 to 20 6 to 6 Connection To AModem 08 9 08 25 Connector Connector 3 to 2 2 to 3 7 to 4 8 to 5 6 to 6 5 t...

Page 33: ...MAGE TO MODULE PARTS AVOID TOUCHING AREAS OF INTEGRATED CIRCUITS STATIC DISCHARGE CAN DAMAGE THESE CIRCUITS b The MVME135 136 may be installed into any double high slot on a VMEmodule chassis Make certain that the intended slot does not have I O cabling on P2 since that could potentially damage the MVME135 136 VSBbus interface c Using a firm grip on the module slide the unit into the card slide un...

Page 34: ...y are described below Table 3 1 provides the MVME135 136 module status for all possible combinatior s of these LEOs The FAIL indicator 051 is a discrete red LED that indicates the status of the BOFAIL software bit The HALT indicator 052 is a discrete red LED that indicates when the halt line of the MPU is asserted The HALT indicator may flicker as a result of normal CPU operation The RUN indicator...

Page 35: ...ING INSTRUCTIONS LED INDICATORS ABORT I RESET PUSHBOTTONS MAPPING SWITCH 53 SYSTEM CONFIGURATION SELECT SWITCH 54 DB 9 SERIAL PORT CONNECTORS e BORT 0 ESET 0 I I I J6 U e FIGURE 3 1 MVMEl35 136 FRONT PANEL 3 2 ...

Page 36: ...dicator is also ON if the MVMEl35j136 is the system controller and SYSFAI L is detected low on VMEbus MPU is halted and BRDFAIL has not been cleared since reset or has been set by software The FAIL indicator is also ON if the MVME135 136 is the system controller and SYSFAIL is detected low on VMEbus MPU is runn in9 and encounteri n9 VMEbus deadlocks and or PMMU relinquish and retry The frequency o...

Page 37: ... A14 A09 AOO A07 X X x tX GROUP SELECT BASE OFFSET MPCSR BASE ADDRESS SWITCH S3 01010101010101010 DRAM BASE AODAESS1tf FIGURE 3 2 MVME135 135 1 136 SLAVE ACCESS ADDRESSING AOO 0 o o 0 0 i z Cl z V l i 0 c i o z V l ...

Page 38: ...ion NOTE ON is 0 OFF is 1 11111010101010101 MPCSR Located In VMEbus Short I O Space SFFFF XXXX Base Addr 1 1 0 0 0 0 0 0 0 0 0 0 0000 SC000 DRAM Base Addr 0000 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 S0000 0000 Example 2 MVME135 135 1 136 versions only Switch S3 Mapping Switch NOTE ON is 0 OFF is 1 MPCSR Base Addr 1 1 0 0 0 0 0 0 0 1 0 0 0000 SC040 DRAM Base Addr 0000 0 0 0 0 0 0 1 0 0000 0000 00...

Page 39: ...e Addr 1 1 0 0 0 0 0 0 0 1 1 0 0000 SC060 DRAM Base Addr 0000 0 0 0 0 0 0 1 1 0a00 0000 0000 0000 0000 0030 0000 Example 4 MVME135 135 1 136 versions only 101 0 I 0 I 1 I 0 I 0 101 1 I MPCSR Switch S3 Mapping Switch NOTE ON s 0 OFF is 1 Base Addr 0 0 0 0 0 0 1 0 0 0 1 0 0000 S0220 DRAM Base Addr 0000 0 0 0 1 0 0 0 1 0000 0000 0000 0000 0000 S0110 0000 3 6 ...

Page 40: ...l MPCS BASE ADDRESS lNSHORT 1 0 ADDRESS SPACE A15 AOO X 0 GROUP SELECT BASE OFFSET MPCSR BASE ADDRESS SWITCH S3 FIGURE 3 3 MVME135A 136A SLAVE ACCESS ADDRESSING w a 0 l i Z G z Vl i 0 C n i a z Vl ...

Page 41: ...i ng Switch Factory Configuration NOTE ON is 0 OFF is 1 MPCSR Located In VMEbus Short I O Space SFFFF XXXX Base Addr 1 1 0 0 0 0 0 0 0000 C000 DRAM Base Addr 0000 0 0 0 0 0 0 0 0 0e00 0000 0000 0000 0000 0000 0000 Example 2 MVME135A 136A versions only MPCSR Switch S3 Mappi ng Switch NOTE ON is 0 OFF is 1 Base Addr 1 1 0 0 0 0 0 0 0 1 0 0 0000 C040 DRAM Base Addr 0000 0 0 0 1 0 0 0 0 00 0 0 00 0 00...

Page 42: ...Addr 1 1 0 0 0 0 0 0 0 1 1 0 0000 C060 DRAM Base Addr 0000 0 0 0 0 1 1 0 0 0000 0000 0000 0000 0000 S00C0 0000 Example 4 MVME135A 136A versions only O F U U 012345678 10101011101010111 MPCSR Switch S3 Mappi ng Switch NOTE ON s 0 OFF s 1 Base Addr 0 0 0 0 0 0 1 0 0 0 1 0 0000 0220 DRAM Base Addr 0000 0 1 0 0 0 1 0 0 0000 0000 0000 0000 0000 0440 0000 3 9 I ...

Page 43: ...L Ss4 10 OFF Autoboot enabled ON Autoboot disabled 4 9 OFF MP bits enabled ON MP bits disabled S4 8 S4 7 S4 6 S4 5 S4 4 S4 3 S4 4 S4 3 S4 4 S4 3 S4 4 S4 3 S4 2 S4 1 OFF VSBbus disabled ON VSBbus enabled OFF VSB not system controller ON VSB is system controller OFF 24 bit VMEbus addr width ON 32 bit VMEbus addr width OFF 16 bit VMEbus data width ON 32 bit VMEbus data width ON 135bug executes 1oca11...

Page 44: ... 3 2 FC2 FCI FC0 1 o TABLE 3 2 FUNCTION CODE ASSIGNMENTS Cycle Type Reserved User Data User Program Reserved Reserved Supervisory Data Responding Board Devices Functions None causes 1oca1 timeout All except the interrupt handler MC68851 and MC68881 All except the interrupt handler MC68851 and MC68881 None causes local timeout None causes local timeout All except the interrupt handler MC68851 and M...

Page 45: ...B003B FFFB003C FFFB003F FFFB0040 FFFB004F On board DRAM On board ROM PROM EPROM Not Used MVSB2400 VSB Gate Array Z8036 Ti mer STAll CNll Not Used STAT2 Not Used CNT2 CNT3 CNT4 CNT5 Not Used MC68681 Serial Controller Port Size Size Bytes 032 016 1Mb 032 016 15Mb 032 4Gb 032 016 N A 016 008 N A 008 N A 008 008 008 008 N A 038 1Mb 128Kb 512Kb 64Kb 64Kb 2b Ib 4b Ib Ib Ib 1b 4b 16b FFFB0050 FFFB005F No...

Page 46: ... FFF9FFFF Not Used N A 1Mb FFFA00130 FFFAFFFF MVSB24ee VSB Gate Array 016 64Kb FFFB0000 FFFB002F Z8036 Timer STATl CNTl 008 64Kb FFFBe030 FFFBee31 Not Used N A 2b FFFB0032 STAT2 008 Ib FFFBe1333 FFFB0037 Not Used N A 4b FFFB131338 CNT2 0138 Ib FFFB13039 CNB 0138 Ib FFFB1303A CNT4 0138 Ib FFFB1303B CNT5 008 Ib FFFB1303C FFFB1303F Not Used N A 4b FFFB1313413 FFFB1304F MC6868i Serial Controller 008 1...

Page 47: ...OPERATING INSTRUCTIONS I 3 14 ...

Page 48: ...in ROM PROM EPROM sockets VMEbus system controller functions a seven level VMEbus interrupt handler and a dual ported high level communication interface call ed the Mul t i processor Control and Status Regi sters MPCSR 4 2 1 Data Bus Structure The data bus structure on the MVME135 136 modul e is arranged to accommodate the 8 bit 16 bit 32 bit and 16 32 bit ports that reside on the module The 8 bit...

Page 49: ... I N VMEbus EXTENDED VMEbus I VSBbus FIGURE 4 1 MVMEI35 135 1 136 BLOCK DIAGRAM C Z n l o z r o VI n 0 t J l o Z ...

Page 50: ... l o w VMEbus EXTENDED VMEbus VSBbus FIGURE 4 2 MVME135A 136A BLOCK DIAGRAM II c z n l o z r o rr1 V n x J l o z ...

Page 51: ... 67 MHz 20 00 101Hz 16 57 101Hz 16 57 MHz 16 67 101Hz WRITE READ WRITE READ WRITE READ WRITE READ WRITE READ MPU TO LOCAL DRAM 3 3 3 3 4 4 4 4 5 5 NO PARITY MPU TO LOCAL DRAM 4 4 4 4 4 4 5 5 5 5 PARITY ENABLED MPU TO LOCAL ROM B B 9 9 9 PROM EPROM VMEbua TO LOCAL 11 10 11 11 11 10 12 11 12 11 DRAM MPU TO GLOBAL DRAM OVER VSB B B 9 9 B B 9 9 9 9 MVME204 2F MPU TO GLOBAL DRAM OVER VMEbua 9 10 12 14 ...

Page 52: ...PU clock period in nanoseconds and N is the total number of MPU clock periods required to complete a VMEbus cycle Nmust always be rounded to to the next integer For read accesses For write accesses N 6 Tac Tr T N 7 Tac Tr T typical typical The following formula assumes that the MVME135 136 module is NOT the current VMEbus master and it is NOT the system controller Also it assumes that all previous...

Page 53: ...fectively eliminating all alignment restrictions Refer to the MC68020UM AD User s Manual for a detailed description of its operation 4 4 MC68881 FPCP The MVMEI35 135A 136 136A versions are equipped with a 16 67 MHz MC68881 Floating Point Coprocessor On the MVME135 1 version the MC68881 operates at 20 00 MHz The MC68881 extends the main MPU integer data processing capabilities It does this by provi...

Page 54: ...upies 64 I O pins on connector P2 and utilizes the multiplexing of address and data in order to accommodate full 32 bit functionality along with appropriate control signals within the 64 pin allotment On the MVME135 136 modules VSBbus is implemented through the use of the MVSB2400 The MVSB2400 is a 132 pin gate array subset of the VSBbus specification in a PGA package The MVSB2400 provides most of...

Page 55: ... only to determine the address of the DRAM but is also used to determine the location at which the Multiprocessing Control Status Register MPCSR is located This mapping is explained in detail in section 4 16 and mapping examples are provided in section 3 2 4 On board DRAM responds to a VMEbus access only when address modifier lines AM through AMS indicate extended or standard privileged or non pri...

Page 56: ...19 __ Al 6rA 15 ________________________ A OO I 0 1 1 1 I Ix x x x x x x x x x x x ITYPE FIELD I I CPU SPACE TYPE FIELD CPU SPACE TRANSACTION AID A16 o 0 0 0 BREAKPOINT ACKNOWlEOGE 000 1 ACCESS LEVEL CONTROL o 0 1 0 COPROCESSOR COMlolUNICATlONS 1 1 1 1 INTERRUPT ACKNOWLEDGE FIGURE 4 3 CPU SPACE TYPE FIELD ENCODING 4 10 1 MC68851 Breakpoi nt Support In order to simplify debugging and emulation for ...

Page 57: ...t register pairs a replacement opcode corresponding to the breakpoint number place this opcode on the processor data bus and assert the DSACK signal The processor then replaces the breakpoint opcode in its instruction pipeline with the new opcode supplied by the MC68851 and continues execution The systems programmer has full discretion to design the actions initiated by execution of the replacemen...

Page 58: ... Each of the breakpoint acknowledge data registers BAD0 through BAD7 can be loaded with a replacement opcode for transfer to the MC68020 during the MC68851 acknowledge cycle Using the PMOVE instruction the 16 bit value for a legal MC68020 opcode may be written to or read from any BADx register in the format illustrated in Figure 4 6 15 BAD REPLACEMENT OPCOOE FIGURE 4 6 BREAKPOINT ACKNOWLEDGE DATA ...

Page 59: ...of the eight acknowledge control registers Refer to the NC68851 User s Manual for a more detailed description of the MC68851 breakpoint registers and functions 4 10 5 Access Level Control For communications between the MC68020 and the MC68851 during the Access level Control ACL type of CPU space operations the PMMU has an interface that includes a register set and support for a communications prot...

Page 60: ...DE I DESCRIPTOR ADDRESS USER DATA WRITE I 10010x FUNCTION CODE 2 DESCRIPTOR ADDRESS USER PROGRAM WRITE I 0 0 I I x FUNCTION CODE 3 DESCRIPTOR ADDRESS USER RESERVED WRITE 10100 x FUNCTION CODE 4 DESCRIPTOR ADDRESS SUPERVISOR DATA WRITE I I I 0 I 0 I x FUNCTION CODE 5 DESCRIPTOR ADDRESS SUPERVISOR PROGRAM WRITE I I 0 I I 0 FUNCTION CODE 6 DESCRIPTOR ADDRESS WRITE 1 0 1 1 1 x x IFUNCTION CODE 7 DESCR...

Page 61: ...and the MC68881 User s Manual TABLE 4 4 MC68851 COPROCESSOR INTERFACE REGISTER MAP A04 AOO MC68851 ACCESS LEVEL INTERFACE REGISTER IN BINARY 31 15 0 o 0 0 0 RESPONSE READ 00 0 1 CONTROL WRITE 001 O SAVE READ o 0 1 1 RESTORE READ I WRITE 01 00 OPERATION WORD WRITE o 1 0 1 COMMAND WRITE 01 1 0 x RESERVED o 1 1 1 CONDITION WRITE 1 00 x x OPERAND READ I WRITE 1 0 1 x x REGISTER SELECT READ RESERVED J ...

Page 62: ...ches the appropriate exception vector number from PROM and sends it to the CPU via the local bus If the interrupt being acknowledged is a Group 1 interrupt the exception vector number is fetched from the VMEbus where it will be placed by the interrupting device Table 4 6 describes the interrupt assignments TABLE 4 6 INTERRUPT HANDLER PRIORITY ASSIGNMENTS PRIORITY WITHIN A PARTICULAR INTERRUPT LEVE...

Page 63: ...erial port chip the MC68681 The SIOIRQ interrupt is handled the same as all other local interrupts where the vector is suppl ied by a PROM SIGHP MPCSR High Priority IRQ SIGHP is the signal high priority interrupt from the MPCSR This interrupt is maskable using the SHPIEN bit of CNT3 VSBIRQ VSBbus IRQ VSBIRQ is an interrupt from the secondary bus VSBbus This interrupt is maskab1e using the VSBIEN b...

Page 64: ...standard RS 232C drivers and receivers Signals are available through DB 9 connectors located on the MVME135 136 module s front panel Both ports are configured as a 9 wire DTE interface as illustrated in Figure 4 10 SERIAL PORT 1 SERIAL PORT 2 1 OCO DeO 2 RXO RXO J TXO TXO 4 OTA OTA 5 SG SG 6 OSR DSR 6 7 RTS RTS 7 8 CTS g FG CTS I FG FIGURE 4 10 SERIAL PORT INTERCONNECTIONS 4 14 MVME135 136 TIMER T...

Page 65: ...ystem controller functions are independent of local reset the MVME135 136 modules will not assert the SYSRESET signal on the VMEbus when either of the local reset options is chosen Two types of local reset are available from the watchdog reset timer and are enabled via bits 6 and 7 WD WDl of Local Control Register 5 They are a r 10mentary Reset of sufficient duration to reset all hardware on the m...

Page 66: ... used for software steering Access to this register will read Port A of the timer 135bug configures Port A of the timer as an input port and uses these general purpose bits to perform various optional switching functions For a complete description of 135bug s use of these switches refer to the 135bug Diagnostic Debug Package User s Manual If firmware other than 135bug is used the resident firmware...

Page 67: ...sing a retry The MC68020 terminates the cycle and then arbitrates the local bus away allowing the slave access to complete After the slave access has completed and the MC68020 becomes the local bus master the retry cycl e then compl etes all transparent to the system software RMCERR indicates that the lockup condition described above has occurred while the local MC68020 was executing a TAS Test An...

Page 68: ...rent logical bus master to terminate the current bus cycle release the logical bus and retry the bus cycle when it is once again logical bus master The concurrent assertion of HALT and BERR by the MMU constitutes the Retry phase of the Re1 inquish and Retry cycle The MMUBER status bit will only indicate true MMU cycle faults not Relinquish and Retry cycle types LCLERR Local Timeout Error LCLERR wh...

Page 69: ...I interrupt The Timer I O pin connected to VMEbus IRQl must never be programmed as an output Timer port B bit 7 WWP Write Wrong Parity WWP when high forces parity to be written incorrectly to local DRAM This facil itates testing of on board parity circuitry PAREN Pari ty Enabl e PAREN when low enables parity error reporting by allowing bus errors to the local processor on read cycles where parity ...

Page 70: ...D Software steering bit that shows the module s system readiness BUSY is used by 135bug as a status flag during diagnostic operation BUSY is imaged in a read only register in the MPCSR refer to section 4 16 ALLIEN All Interrupt Enable When ALLIEN 0 all MVME135 136 interrupts are enabled to the Interrupt Handler When ALLIEN 1 all interrupts are disabled allowing vector table initialization SYSFI EN...

Page 71: ...n the MPCSR refer to section 4 16 BRIRQO Broadcast Interrupt Output BRIRQO when low asserts VMEbus IRQ1 This is not intended to cause a VMEbus interrupt This bit is intended for use as a broadcast mechanism that is compatible with the MVME13 where VMEbus IRQ1 is connected to bit 7 of Timer Port B and causes a timer interrupt The MVME135 136 is also capable of being interrupted in this way Refer to...

Page 72: ...at 00000000 hex The local DRAM always appears at FFE00000 hex for the MVME135 135 1 l36 versions and at FF800000 hex for the MVf1E135A 136A versions 32 24 VMEbus Address Si ze Sel ect This bit provides a software selectable 32 and 24 bit address option for VMEbus references The appropriate address modifiers are generated for 32 or 24 bit address VMEbus accesses 32 24 1 indicates 32 bit address opt...

Page 73: ...en 32 16 0 all memory references to VMEbus are forced to be 16 bits When 32 16 1 all memory references to the VMEbus can be 32 bits The memory map can be customi zed in hardware by the user to segment 016 and D32 address space This is performed by programming PAL2 U60 for the particular application The default memory map for 032 and 016 data space is illustrated in Figure 4 11 Refer to Appendix A ...

Page 74: ...this type of environment These include global access to and control of the status of several modul e funct ions as well as the abil ity to generate virtual interrupts to selected boards and or simultaneous interrupts to multiple boards Their design does not define or limit in any way the architecture of a multiprocessor application but rather eases its development particularly from the point of vi...

Page 75: ...allows the local processor to i dent i fy where other bus masters wi 11 be access i ng its memory The MPCSR will be at xxxyyyyy on the VMEbus where xxx is the group base address and yyyyy is the base offset within the group The module 10 can be read visually from the board by looking at the 8 bit mapping switch S3 Refer to the Local DRAM and MPCSR Mapping examples in section 3 2 4 BSY Busy Bi t Th...

Page 76: ...modules in the group at the same time LH0 LH2 Location Monitor Bits The local processor can be interrupted by a broadcast cycle This cycle can be recognized by all MVME135 136s in the system This is accomplished with a location monitor that will detect a VMEbus cycle to the Al6 Short I O addresses determined by the VMEbus mapping switch There is an enable bit in the local CSR CNB that will allow t...

Page 77: ... E 0 0 000 RESERVED FOR BROADCAST GROUP 1 4000 0000 o 0 0 0 4 020 0 0 1 0 o 0 0 0 404 0 s 0 0 2 0 o 0 0 0 4 8 0 4 A 0 4 3 C 0 01CO 0000 01000000 S01EO 0000 RESERVED FOR BROADCAST GROUP 2 6000 00000000 6 0 2 0 0 0 1 0 0 0 0 0 6 0 4 0 0 0 2 0 000 0 5 6 3 8 0 5 0 1 COO 0 0 0 Sl 3AO 01000000 6 3 C O O l E 0 000 0 RESERVED FO BROADCAST GROUP 3 NOTE SErnNG S3 4 THROUGH S3 8 TO 1 ALL OFF IS NOT ALLOWED 0...

Page 78: ...is more efficient because the total number of VMEbus arbitration cycles is reduced R H Reset and Hol d Bi t Another VMEbus master will be able to place the module in reset by asserting this bit location The module will remain in reset until the location is cleared or a system reset occurs When R H is set a minimum of 5 microseconds may elapse before the module is placed in reset When R H is cleare...

Page 79: ...ters that will allow this interrupt to occur SLPIEN in eNT3 This is a level 2 interrupt to the local processor SIGHP Signal High Priority The local processor may be interrupted by asserting this bit location There is a control bit in the local CSR that will allow this interrupt to occur SHPIEN in CNT3 This signal is a higher priority locally level 5 than SIGLP MP0 MP3 Mul t i Processor Bi ts These...

Page 80: ...he block transfer count extended address register This register is referred to as the VSBCSR VSBbus Regi ster o 1 2 Function Control and Status Block Transfer Extended Address Decode Address Not used and should not be accessed on the MVME135 136 4 17 1 VSBbus Control Status Reg ster Format And Funct ons This register controls those functions which if asserted could drastically affect the functioni...

Page 81: ...PING SWITCH EXAMPLE SWITCH 53 F NOTE OH O OFF 1 1 2 3 4 5 678 GROUP 1 1 0 6 11 11 10 10 10 10 11 10 1 Y yt t rrl MPCSR BASE ADDRESS 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 DRAM BASE ADDRESS 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIGURE 4 12 MPCSR AND DRAM ADDRESS MAPPING AOO o C z n o z r C1 rTl Vl n 0 o z ...

Page 82: ...e AS signal to generate the PAS signal without waiting for QAS thus allowing decode on VSBbus slaves to determine which bus VSBbus or VMEbus will be used If a VSBbus slave is not found the cycle is automatically directed to VMEbus Bi t 05 READONLY VSBbus Read Only READONLY prevents writes from occurring on the VSBbus from this master Write cycles are automatically directed to VMEbus for cache moni...

Page 83: ...s shared equally among VSBbus masters that all have fairness mode When ROBIN is negated the bus bandwidth is prioritized by a daisy chain scheme where the modules closest to the system controller will receive most of the available bus bandwidth Bit 11 WRERROR Wr te Error status Bit WRERROR reports the fact that a write to a read only bus was attempted Bit 12 BUSTIMEOUT VSBbus Timeout BUSTIMEOUT re...

Page 84: ...VSBbus sl ave devices It is important to note that when a ribbon cable is used at least one of the slave devices must connect VSB BGIN to VSB BG P2 A31 to P2 C32 VSBbus backplanes are available in varied configurations typically up to six slots These backplanes plug into P2 connectors on the VME P2 backplane VSBbus backplanes are needed for applications requiring more than two VSBbus masters The b...

Page 85: ...FUNCTIONAL DESCRIPTION I 4 38 ...

Page 86: ...135 136 module The pin connections VMEbus signal mnemonics and signal descriptions for the PI connector are provided in Table 5 1 Refer to the ANSI IEEE Standard HH4 1987 Versatile Backplane Bus VMEbus for a complete description of the VMEbus signals Pin Number AI A8 A9 AHI All AI2 TABLE 5 1 CONNECTOR PI INTERCONNECT SIGNALS Si gna1 Mnemonic 000 007 GND SYSCLK GND DSI Signal Name and Description D...

Page 87: ...GE An open collector driven signal generated by a data transfer bus slave The falling edge of this signal indicates that valid data is available on the data bus duri ng a read cycle or that data has been accepted from the data bus duri ng a write cycle GROUND ADDRESS STROBE The falling edge of this signal is used to indicate that a valid address is on the address bus AS is an active low TTL three ...

Page 88: ... 3 are used to indicate the interrupt level that is being acknowledged 12 Vdc POWER Used by system logic circuits 5 Vdc POWER Used by system log icc i rcu its VMEbus BUSY An open collector driven signal generated by the current Data Transfer Bus DTB master to indicate that it is using the bus NOT CONNECTED SYSTEM AC POWER FAIL An open collector driven signal which indicates that the AC input to th...

Page 89: ... master in the daisy chain requires access to the bus BUS REQUEST level 1 Same as BR on pin B12 BUS REQUEST level 2 Same as BR on pin B12 BUS REQUEST 1 eve1 3 Same as BR on pin B12 ADDRESS MODIFIER bits 3 Same as AM4 on pin A23 GROUND NOT CONNECTED GROUND 824 83 IRQ7 IRQl INTERRUPT REQUEST bits 7 1 These signals are generated by an interrupter and carry the prioritized interrupt requests Level 7 i...

Page 90: ...ollector driven signal generated by a slave BERR indicates that an unrecoverable error has occurred and the bus cycle must be aborted SYSTEM RESET An open collector driven signal which when low will cause the system to be reset l ONGW ORD A three stilte driven signal specifying that the cycle is a byte word transfer when high or a 10ngword transfer when low ADDRESS MODIFIER bit 5 Same as AM4 on pi...

Page 91: ...r receive addresses and data over the VSBbus All lines are active high TTL three state signals VSBbus MULTIPLEXED ADDRESS DATA bit 02 Same as MAD00 on pi nAI VSBbus MULTIPLEXED ADDRESS DATA bit 04 Same as MAD00 on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 06 Same as MAD00 on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 08 Same as MAD00 on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 10 Same as MAD00 ...

Page 92: ...L open collector signal VSBbus DATA STROBE The fa11 ing edge of MDS indicates that a valid data transfer will occur on the bus MAD00 to MAD31 at this time During write cycles write data is valid at the falling edge of MDS This line is an active low TTL three state signal VSBbus WRITE This signal when low indicates that a write operation is to be performed and when high indicates that a read operat...

Page 93: ...ine is an active low TTL open collector signal GROUND VSBbus GRANT IN This input signal is generated by the arbiter or a requester The bus grant in and bus grant out signals form a bus grant daisy chain MBGIN indicates to the module receiving it that it may use the VSBbus VSBbus REQUEST This signal is an output from the requester and an input to the arbiter when system controller and to the reques...

Page 94: ...t of the 16 bidirectional three state driven data lines which provide the expanded data path between the DTB master and slave for the optional expanded data bus configuration GROUND 5 Vdc POWER Used by system logic circuits VSBbus MULTIPLEXED ADDRESS DATA bit 01 Same as MAD00 on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 03 Same as MAD00 on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 05 Same as MAD...

Page 95: ...on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 27 Same as MAD00 on pin AI VSBbus MULTIPLEXED ADDRESS DATA bit 29 Same as MAD00 on pi n AI VSBbus MULTIPLEXED ADDRESS DATA bit 31 Same as MAD00 on pi n AI GROUND VSBbus SIZE bit 0 One of two lines which in conjunction with MAD00 and MAD01 determine the active portion of the data bus This line is an active low TTL three state signal VSBbus ADDRESS STROB...

Page 96: ...f the data bus for the slave module Finally ASACK can be gated with signal AC on the master device The condition of AC active and ASACK inactive while MAS is asserted is defined to indicate that no VSBbus slave module has decoded the address being driven at that time or that there are no VSBbus slave modules installed This provides the VSBbus master the opportunity to switch to the VMEbus when VSB...

Page 97: ...ltant rising edge causes the arbiter to sample the bus request line and grant the bus to the requester This line is an active low TTL open collector signal VSBbus GRANT OUT This line is the output of the on chip requester MBG is asserted whenever the module receives a bus request and is the system contro11 er and does not need the bus or when it is not the system controller and it receives a bus g...

Page 98: ... causes data to be written into local data bits LD08 through LOIS DRAM WRITE ENABLE BYTE 0 This signal when asserted causes data to be written into local data bits LD00 through LD07 DRAM COLUMN ADDRESS STROBE BYTE 3 This signal when asserted strobes column addresses to local DRAMs connected to data bits LD24 through LD31 DRAM WRITE ENABLE BYTE 2 Th iss i gna1 when asserted causes data to be writte...

Page 99: ... 26 27 5 14 REFRAS NORMRAS ROWADDR MEZZERR DRAM REFRESH ROW ADDRESS STROBE REFRAS is logically OR ed with NORMRAS with timing to perform CAS before RAS refresh NORMAL DRAM CYCLE ROW ADDRESS STROBE This DRAM address multiplexed control signal is used as a timing strobe for normal memory cycles ROW ADDRESS SELECT This signal is used to switch from row to column addresses on the DRAM Mezzanine MEZZAN...

Page 100: ...connected directly to the MC68 2 microprocessor LOCAL DATA BUS bit 24 Same as LD16 on pin l LOCAL DATA BUS bit 17 Same as LD16 on pin l LOCAL DATA BUS bit 25 Same as LD16 on pin 1 LOCAL DATA BUS bit IS Same as LD16 on pin l LOCAL DATA BUS bit 26 Same as LD16 on pin 1 LOCAL DATA BUS bit 19 Same as LD16 on pin 1 LOCAL DATA BUS bit 27 Same as LD16 on pin 1 5 Vdc POWER Used by system logic circuits GR...

Page 101: ...TA BUS bit 13 Same as LD16 on pin l LOCAL DATA BUS bit 28 Same as LD16 on pin 1 GROUND 5 Vdc POWER Used by system logic circuits NOT CONNECTED PHYSICAL ADDRESS bit 21 One of 2 physical address lines used to address memory locations contained on the MVME135 136 DRAM mezzanine module NOT CONNECTED PHYSICAL ADDRESS bit 19 Same as PA21 on pin 27 PHYSICAL ADDRESS bit 2 Same as PA21 on pin 27 PHYSICAL A...

Page 102: ... Same as PA2l on pin 27 42 PA06 PHYSICAL ADDRESS bit 06 Same as PA2l on pin 27 43 PA12 PHYSICAL ADDRESS bit 12 Same as PA2l on pin 27 44 PA13 PHYSICAL ADDRESS 27 bit 13 Same as PA21 on pin 45 PA10 PHYSICAL ADDRESS 27 bit 10 Same as PA21 on pin 46 PAll PHYSICAL ADDRESS 27 bit 11 Same as PA2l on pin 47 PA08 PHYSICAL ADDRESS bit 08 Same as PA2l on pin 27 48 PA09 PHYSICAL ADDRESS 27 bit 09 Same as PA2...

Page 103: ...rols the parity generate detect mode on the DRAM mezzanine module NOT CONNECTED DRAM PARITY ENABLE This signal when asserted allows the DRAM mezzani ne modul e to report pari ty errors on detection via the MEZZERR signal WRITE WRONG PARITY This signal when asserted forces the DRAM mezzan i ne modul e into a diagnostic mode where parity is intentionally wri tten incorrectly for test i ng purposes ...

Page 104: ...modulated from the receiver line is presented to the termi naI by the modem DATA TERMINAL READY channel B This signal from the terminal to the modem indicates that the terminal is ready to send or receive data SIGNAL GROUND DATA SET READY channel B DSRB is a function supplied by the modem to the terminal to indicate that the modem is ready to transmit data REQUEST TO SEND channel B RTSB is supplie...

Page 105: ...hat is demodulated from the receiver line is presented to the terminal by the modem DATA TERMINAL READY channel A This signal from the termi na1 to the modem ind icates that the terminal is ready to send or receive data SIGNAL GROUND DATA SET READY channel A DSRA is a function supplied by the modem to the terminal to indicate that the modem is ready to transmit data REQUEST TO SEND channel A RTSA ...

Page 106: ... 136 versions not using the PMMU device These lists reflect the latest issue of all MVME135 136 hardware at the time of the printing of this user s manual TABLE 5 7 MVME135 136 PARTS LIST Reference Motorola Designat ion Part Number Description CI 14 CI8 21 C26 32 C34 39 C42 C43 C45 47 C48 52 C15 C17 C16 C33 C44 C22 25 C4 C41 84 W8440B 1 Printed wiring board assembly MVME135 136 used on MVME135 135...

Page 107: ...135 1 only DL4 01NW9804D53 Delay module 125 nsec used on MVME135A only 09NW9811A29 Socket IC OIL 14 pin l req d use at DL4 DSl DS2 48NW9612A49 LED red DS3 48NW9612A59 LED green J3 28NW9802H08 Connector single row 27 pin J4 28NW9802Hl0 Connector double row 56 pin J7 28NW9802D86 Connector single row 3 pin J8 28NW9802D86 Connector single row 3 pin used on MVHE135A only J9 JHl 28NW9802G79 Connector ri...

Page 108: ...etwork seven 113K ohm R20 R21 51NW9626A75 Resi stor network eight 330 4713 ohm 09 W4659810 Socket IC SIL 10 pin 2 req d used at R20 and R21 R23 51NW9626804 Resistor network seven 2K ohm R24 51NW9626A84 Res i stor network fi ve 330 ohm R25 51NW9626A40 Resistor network five lK ohm used on MVME135A only R26 51NW9626856 Resistor network nine 113K ohm used on MVME135A only SI S2 413NW9801B70 Switch pus...

Page 109: ... U13 U14 51AW4804C27 IC Programmed PAL 13 U15 51AW5239B01 IC Programmed PAL 34 used on MVME135 135 1 136 136A only U15 51AW5239B06 IC Programmed PAL 34 used on MVME135A only U16 51AW5471B01 IC Programmed PAL 12 U17 51AW5243B02 IC Programmed PAL 32 U18 51AW5238B02 I C Programmed PAL 7 U19 51 W5552B06 IC Programmed PAL 10 U20 U27 51NW9615F38 IC SN74LS393N U21 51NW9615G81 IC SN74LS132N U22 51AW5120B8...

Page 110: ...II U32 51AW55ril8Brill IC Programmed PAL 24 U33 51AW524rilBril5 IC Programmed PAL 36 U34 U46 51NW9615K47 IC 74F244PC U87 ril9 W4659Blril Socket IC SIL lril pin 1 req d used at U8 used on MVME135A only U35 U92 51NW9615Fril2 IC SN74LS244N U36 51AW5243Bril3 IC Programmed PAL 19 U37 51AW5241Bril2 IC Programmed PAL 18 U38 51NW9615K69 IC 74FlrilPC U39 51NW9615K65 IC 74FllPC U4ril U79 51NW9615J39 IC 74F7...

Page 111: ...used at U50 U51 51NW9615K71 IC 74F04PC U52 51NW9615K73 IC 74F00PC U53 51NW9615C60 IC MC3456P U57 51AW5011B10 IC Programmed PAL 30 09NW9811B01 Socket IC OIL 24 pin 1 req d used at U5 U58 51AW5388B01 IC Programmed PAL 29 09NW9811 B01 Socket IC OIL 24 pin 1 req d used at U58 used on MVME135 135 1 136 136A onl y 09 W4659B12 Socket IC SIL 12 pin 1 req d used at U58 used on MVMEl35A only U59 51AW4697B68...

Page 112: ...ed at U62 U63 U74 51NW9615K7 IC 74F 8PC U64 1 W3464B01 Printed wiring assembly by pass board used on MVME135 135 1 135A only U64 51NW9615Y22 IC XC68851RC16A used on MVME136 136A on1y 09NW9811B14 Socket IC PGA 144 pin 1 req d used at XU64 U65 51NW9615Tl2 IC MC68881RC16B used on MVME135 135A 136 136A only U65 51NW9615U64 IC MC68881RC20B used on MVME135 1 only 9NW9811A71 Socket IC PGA 68 pin 1 req d ...

Page 113: ... 20 pin 1 req d used at U70 U7l 51AW4591C66 IC Programmed PAL 9 09NW9811A78 Socket IC OIL 20 pin I req d used at U7l U73 51NW9615R89 IC MC68020RC16BE used on MVMEl35 135A 136 136A on1y U73 51NW9615T26 IC MC68020RC20BE used on MVMEl35 1 only 09NW9811B12 Socket IC PGA 124 pin 2 req d used at U73 U74 51NW9615K70 IC 74F08PC used on MVME135A only U75 51NW9615W77 IC XVSB2400 09NW9811B33 Socket IC PGA 13...

Page 114: ...nmed PAL 11 e9NW9811A78 Socket IC OIL 2e pin 1 req d used at U83 U84 51 W5449B34 IC Programmed PAL 6 e9NW9811A78 Socket IC OIL 2e pin 1 req d used at U84 U85 51NW9615E96 IC SN74LS245 U86 51AW48e4C31 IC Programmed PAL 1 e9 W4659Ble Socket IC SIL W pin 2 req d used at U86 U89 51NW9615P22 IC HC68681P e9 W4659B2e Socket IC SIL 2e pin 2 req d used at U89 Uge 5INW9615C21 IC SN74LS04N U9I 51NW9615K66 IC ...

Page 115: ...am 1 2 x 1 16 5 inch req d used at Y3 47NW9405A28 Jackpost assembly 2 req d 29NW9805B17 Jumper insulated shorting 10 req d used at J2 l 2 5 6 7 8 9 11 10 12 16 18 J6 1 2 J7 2 3 J12 1 2 J13 4 6 29NW9805B17 Jumper insulated shorting 1 req d used at J8 1 2 USed on MVMEl35Aj136A only 67NW9415A17 Kit 6 component ejector handl e 1 req d 33 W5089B35 Nameplate MVME135 l req d used on MVME135 only 33 W4577...

Page 116: ...1Mb 70 nanosecond I 1 req d used wi th MVMEl35 136 on1 y 01 W3443B02 Printed wiring board assembly mezzanine 1Mb 60 nanosecond Ireq d used with MVME135 1 only 01 W3486B01A Printed wiring board assembly mezzanine 4Mb 100 nanosecond 1 req d used with MVME135A 136A only 42NW9401B14 Screw captive coll ar 2 req d 03NW9004B48 Screw captive M2 S 2 req d 09 W4659B14 Socket IC SIL 14 pin 2 req d used at U5...

Page 117: ...SUPPORT INFORMATION I 5 32 ...

Page 118: ...N 16 FEED PIN PA20 1 0 PIN 17 FEED PIN PA2l 110 PIN 18 FEED PIN RAMSELl 0 PIN 19 NEG PALOW PA3l PA30 PA29 PA28 PA27 PA26 PA2S PA24 PAHI PA3l PA30 PA29 PA28 PA27 PA26 PA2S PA24 EQUATIONS 24ADDR PALOW VSBVME PA22 RAMSELl PAHI PA23 PA22 PA2l PA20 OPT0 PALOW PA23 PA22 PA21 PA20 SEGMENT PAHI PA23 PA22 PA2l PA20 UPPERIMB PAHI PA23 PA22 PA21 PA20 CHECKSUM 2ACF VSBVME MUST BE LOW TO DECODE VME ACCESSES AD...

Page 119: ...bit Refer to the description of CNT5 in the MVME135 136 hardware manual This bit is provided as an aid to configure mixed A24 and A32 slaves in the same VME chassis Used in conjunction with the VSBOEN bit in the VSBCSR When VSBOEN is low the target bus VME or VSB will depend upon this decode output which when low the bus access will be explicitly VME or when high explicitly VSB The output is curre...

Page 120: ... O PIN 18 FEED PIN RAMSELl 110 PIN 19 NEG PALOW PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PAHI PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 EQUATIONS _24ADDR PALOW VSBVME PA22 RAMSEL1 PAHI PA23 PA22 OPT PALOW PA23 PA22 SEGMENT PAHI PA23 PA22 PA21 PA20 PA31 PA30 PA29 PA28 UPPERIMB PAHI PA23 PA22 PA21 PA2 CHECKSUM 2B9B VSBVME MUST BE LOW TO DECODE VME ACCESSES ADDED 2ND TERM TO SEGt ENT FXXXXXXX IS 016 ON ...

Page 121: ...fect this bit Refer to the description of CNT5 in the MVME135 136 hardware manual This bit is provided as an aid to configure mixed A24 and A32 slaves in the same VME chassis Used in conjunction with the VSBOEN bit in the VSBCSR When VSBOEN is low the target bus VME or VSB will depend upon this decode output which when low the bus access will be explicitly VME or when high explicitly VSB The outpu...

Page 122: ... 00000000 VMEbus mastership must be gained to access this area except for 00000000 to 003FFFFF in option 0 For MVME135A 136A version only DRAM 1Mb see description for options 0 and 1 in section 4 1S 2 CNTS For MVME135 135 1 136 versions on1 y DRAM 4Mb see description for options 0 and 1 in section 4 1S 2 CNTS For MVME13SA 136A version only Local resources lMb minus 64Kb SIO ROM LCLCSR and MPCSR Of...

Page 123: ...Tl I FFFB0030 Not Used FFFB0031 Not Used FFFB0032 STAT2 FFFB0033 FFFB0037 Not Used FFFB0038 CNT2 FFFB0039 CNT3 FFFB003A CNT4 FFFB003B CNT5 FFFB003C FFFB003F Not Used FFFB0040 FFFB004F SID FFFB0050 FFFB005F Not Used FFFB0060 FFFB007F MPCSR FFFB0080 FFFBFFFF Not Used FFFC0000 FFFEFFFF Not Used C 2 ...