Memory Maps
2-4
2
Memory Maps
There are three points of view for memory maps:
❏
The mapping of all resources as viewed by the processor (MPU bus
memory map)
❏
The mapping of onboard resources as viewed by PCI local bus
masters (PCI bus memory map)
❏
The mapping of onboard resources as viewed by VMEbus masters
(VMEbus memory map)
The following sections describe the MVME1603/1604 memory
organization from the above three points of view. Additional, more
detailed memory maps can be found in the Programmer’s Reference Guide
(part number V1600-1A/PG).
MPU Bus Memory Map
The MPU bus memory map is split into different address spaces by the
Transfer Type (TT) signals. The local resources respond to the normal
access and interrupt acknowledge codes.
Normal Address Range
The memory map of devices that respond to the normal address range is
shown in the following tables. The normal address range is defined by the
TT signals on the MPU bus. For the MVME1603/1604, transfer types 0,
1, and 2 define the normal address range. Table 2-1 defines the entire map
($00000000 to $FFFFFFFF). Many areas of the map are user-
programmable, and suggested uses are shown in the table. The cache
inhibit function is programmable in the PowerPC 603/604 microprocessor
MMU. The onboard I/O space must be marked ‘‘cache inhibit’’ and
serialized in its page table. Table 2-2 further defines the map for the local
I/O devices (accessible through the directly mapped PCI Configuration
Space).
Summary of Contents for MVME1603
Page 1: ...MVME1603 MVME1604 Single Board Computer Installation and Use V1600 1A IH4 ...
Page 14: ...xiv ...
Page 156: ...Using the Debugger 5 8 5 ...
Page 176: ...ENV Set Environment 6 20 6 ...
Page 190: ...EMC Compliance B 4 B ...
Page 200: ...Proper Grounding C 10 C ...
Page 222: ......
