2-88
Computer Group Literature Center Web Site
VMEchip2
2
Interrupt Level Register 1 (bits 16-23)
This register is used to define the level of the SYSFAIL interrupt and the
master write post bus error interrupt.
WPE LEVEL These bits define the level of the master write post bus
error interrupt.
SYSF LEVEL These bits define the level of the SYSFAIL interrupt.
Interrupt Level Register 1 (bits 8-15)
This register is used to define the level of the VMEbus IRQ1
edge-sensitive interrupt and the level of the external interrupt.
IRQ1E LEVEL
These bits define the level of the VMEbus IRQ1
edge-sensitive interrupt.
PE LEVEL
Not used on MVME1x7P.
ADR/SIZ
$FFF40078 (8 bits [6 used] of 32)
BIT
23
22
21
20
19
18
17
16
NAME
SYSF LEVEL
WPE LEVEL
OPER
R/W
R/W
RESET
0 PSL
0 PSL
ADR/SIZ
$FFF40078 (8 bits [6 used] of 32)
BIT
15
14
13
12
11
10
9
8
NAME
PE LEVEL
IRQ1E LEVEL
OPER
R/W
R/W
RESET
0 PSL
0 PSL
Summary of Contents for MVME1X7P
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Page 90: ...1 64 Computer Group Literature Center Web Site Programming Issues 1 ...
Page 248: ...3 50 Computer Group Literature Center Web Site PCCchip2 3 ...
Page 286: ...4 38 Computer Group Literature Center Web Site MCECC Functions 4 ...
Page 288: ...A 2 Computer Group Literature Center Web Site Summary of Changes A ...
Page 316: ...Index IN 14 Computer Group Literature Center Web Site I N D E X ...