xi
External Source Vector/Priority Registers ..............................................2-122
External Source Destination Registers ....................................................2-124
Hawk Internal Error Interrupt Vector/Priority Register ..........................2-125
Hawk Internal Error Interrupt Destination Register ................................2-126
Interprocessor Interrupt Dispatch Registers ............................................2-126
Current Task Priority Registers ...............................................................2-127
Interrupt Acknowledge Registers ............................................................2-127
End-of-Interrupt Registers .......................................................................2-128
System Memory Controller (SMC)
Block Diagrams .........................................................................................................3-2
Functional Description ...............................................................................................3-6
Four-beat Reads/Writes ...............................................................................3-6
Single-beat Reads/Writes ............................................................................3-6
Address Pipelining.......................................................................................3-6
Page Holding ...............................................................................................3-7
SDRAM Speeds...........................................................................................3-7
Responding to Address Transfers................................................................3-9
Completing Data Transfers..........................................................................3-9
PPC60x Data Parity ...................................................................................3-10
PPC60x Address Parity .............................................................................3-10
Cache Coherency .......................................................................................3-11
Cache Coherency Restrictions...................................................................3-11
L2 Cache Support ......................................................................................3-11
Cycle Types ...............................................................................................3-11
Error Reporting..........................................................................................3-12
Error Logging ............................................................................................3-13
I2C Byte Write...........................................................................................3-23
I2C Random Read .....................................................................................3-25
Summary of Contents for MVME5100 Series
Page 1: ...MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition ...
Page 16: ...xvi ...
Page 20: ...xx ...
Page 28: ...xxviii ...
Page 62: ...1 34 Computer Group Literature Center Web Site Product Data and Memory Maps 1 ...
Page 278: ...3 88 Computer Group Literature Center Web Site System Memory Controller SMC 3 ...
Page 288: ...4 10 Computer Group Literature Center Web Site Hawk Programming Details 4 ...
Page 320: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...